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SPI Introduction

Last modified by Microchip on 2023/11/09 08:53
Contents

Introduction

Serial Peripheral Interface (SPI) is a synchronous serial communication protocol that can be used for short-distance and high-speed synchronous data transfer between embedded systems. SPI is a three or four-wire bus and SPI devices communicate in full-duplex mode with dedicated channels for transmitting and receiving data.

Advantages

  • Higher speed (20MHz) than I2C (1MHz), SWI (2MHz)
  • Dual, quad SPI up to 144MHz
  • Widely used; NOR flash, EEPROM, EERAM, Serial SRAM, SecureDigital, LCD, ADC, DAC, RTCC
  • Push-pull protocol - no pull-up resistors required
  • Does not use unique addressing
  • Protocol easily performed in software (bit-banged)
  • Transceivers not required

Disadvantages

  • No acknowledgement for received data
  • No formal specification

Description

The SPI bus is a synchronous serial data communication bus that operates in Full Duplex mode, using one channel for transmitting and another channel for receiving data. The devices communicate in a host-client environment, with a single host at a time and one or more clients.

The SPI bus consists of four signal connections:

  • SCK: Serial Clock (output from host)
  • SDO: Serial Data Out (data output)
  • SDI: Serial Data Input (data input)
  • /SS: Serial Select

Note: For SDI and SDO pins, the Input/Output direction is from the perspective of the device in reference. If both sides have MOSI and MISO, connect MOSI to MOSI and MISO to MISO. For client devices, connect SDI to MOSI and SDO to MISO. For host devices, connect SDI to MISO and SDO to MOSI.

The host device is the only one that can generate a clock. Therefore, it is typically the initiator of the data exchange. The SPI host device uses the same SCK, SDO and SDI channels for all the clients, but usually individual lines of SS for each of the clients. However, the daisy-chain feature offers the possibility of using only one SS line to control more than one client device. With either the host or the client device, data is always shifted out one bit at a time, on the programmed clock edge and with the Most Significant bit (MSb) shifted out first. At the same time, a new Least Significant bit (LSb) is shifted into the same register.

SPI Peripheral Block Diagram

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Modes

SPI supports 4 modes. These modes represent the way in which data are transmitted with respect to the clock generation. The clock polarity and the clock edge are the important parameters for data modes. The clock polarity refers to the level of the signal in Idle state. The signal can be either low in Idle state, and start with a rising edge when transmitting data, or high in Idle state and start with a falling edge when transmitting data.

  • SPI modes 0 and 1 SCK idles low:

SPI Modes 0 and 1 SCK Low

  • SPI modes 2 and 3 SCK idles high:

SPI modes 2 and 3 SCK High

  • SPI modes 0 and 3:
    • Sample data on SDI on the rising edge of SCK:

SPI Modes 0 and 3 SDI Sample Timing

  • SPI modes 0 and 3:
    • Output data on SDO on the falling edge of SCK:

SPI Modes 0 and 3 SDO Timing

  • SPI modes 1 and 2:
    • Sample data on SDI on the falling edge of SCK:

SPI Modes 1 and 2 SDI Sample Timing

  • SPI modes 1 and 2:
    • Output data on SDO on the rising edge of SCK:

SPI Modes 1 and 2 SDO Timing

The accompanying image shows comparison for the 4 SPI modes:

Waveforms for the 4 SPI Modes

Note: For modes 1 and 3, data is output on the first clock edge. For modes 0 and 2, data is output on the falling edge of the Serial Select (/SS) pin. 

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Multidrop Configuration

Multidrop configuration uses a dedicated serial select pin for each client node. The host device selects the desired client by pulling the serial select signal low then transfers data to the selected client.

Note: /SS pin(s) are typically driven by a general-purpose input-output (GPIO) pin and do not have to toggle between byte transfers. They can remain low throughout the entire multi-byte transaction then raised to deselect the client node and end the data frame.

SPI Multidrop Block Diagram

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Daisy Chain Configuration

Daisy chain SPI is commonly used in applications where multiple SPI devices need to be connected to a single SPI host, but there are limited available SPI pins. By using daisy chain SPI, multiple devices can be connected in a series, reducing the number of pins and simplifying the overall system hardware design. In this configuration, the output of one device is connected to the input of the next device, and so on. The first device in the chain is the SPI host, which controls the communication between all the devices in the chain.

SPI Daisychain Block Diagram

When data is to be transmitted, the shared /SS connection is driven low and data is sent from the SPI host to the first device in the chain. The first device processes the data and then passes it on to the next device in the chain. This process continues until the data reaches the last device in the chain. The Host transmits data in the reverse order of the daisy chained client nodes. This means the data for the last client node in the chain is transmitted first and the data for the for the first client node is transmitted last. After the number of transfers match the number of client nodes, all client nodes will have received their respective data.

SPI Daisychain Data Flow

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Learn More

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