What is Single Wire Interface (SWI) Protocol?

Introduction

Single Wire Interface (SWI) is a two-pin protocol (SI/O and Ground) that harvests energy from the SI/O pin to power the integrated circuit. The protocol is optimized to add configuration and use information in unpowered attachments using a two-point mechanical connection that brings only one signal (SI/O) and GND to the unpowered attachment. Some unpowered attachment application examples include analog sensor calibration data storage, ink and toner printer cartridge identification, and management of after‑market consumables. The device’s software addressing protocol allows up to eight devices to share a common single‑wire bus.

SWI is structured similarly to I²C with some trade-offs:

Advantages

• Only requires a single data line, which can save on board space and reduce wiring complexity.
• Supports longer distances than I²C, up to several meters.

Disadvantages

• Not as widely used or supported as I²C, which means fewer devices and libraries available.
• Can be more susceptible to noise and interference due to the single wire design.
• Operates at slower speeds than I²C, 3.2 Mbs versus 125 Kbps.

Terminology

• V_PUP: Pull-up Voltage
• R_PUP: Pull-up Resistance
• V_IL: Input Low Voltage
• V_IH: Input High Voltage
• V_OL: Output Low Voltage
• t_RESET: Reset Time Low
• t_DSCHG: Discharge Low Time, Device in Active Write Cycle (tWR)
• t_RRT: Reset Recovery Time
• t_DRR: Discovery Response Request
• t_DACK: Discovery Response Acknowledge Time
• t_MSDR: Host Strobe Discovery Response Time
• t_HTSS: SI/O High Time for Start/Stop Condition
• t_BIT: Bit Frame Duration
• t_HTSS: SI/O High Time for Start/Stop Condition
• t_LOW0: SI/O Low Time, Logic ‘0’ Condition
• t_LOW1: SI/O Low time, Logic ‘1’ Condition
• t_RD: Host SI/O Low Time During Read
• t_MRS: Host Read Strobe Time
• t_HLD0: Data Output Hold Time (Logic ‘0’)

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Description

SWI utilizes a Client device and a single‑wire digital serial interface to communicate with a Host controller, commonly referred to as the bus Host. The Host controls all read and write operations to the Client devices on the serial bus. Devices utilizes an 8-bit data structure. Data is transferred to and from the device via the single‑wire serial interface using the Serial Input/Output (SI/O) pin. Power to the device is also provided via the SI/O pin, thus only the SI/O pin and the GND pin are required for device operation. Data sent to the device over the single‑wire bus is interpreted by the state of the SI/O pin during specific time intervals or slots. Each time slot is referred to as a bit frame and lasts t_BIT in duration. The Host initiates all bit frames by driving the SI/O line low. All commands and data information are transferred with the Most Significant bit (MSb) first. Many SWI components reserve bits in the first byte for opcodes to perform specific actions within the Client device. Refer to the appropriate datasheet for more information.

During bus communication, one data bit is transmitted in every bit frame, and after eight bits (one byte) of data has been transferred, the receiving device must respond with either an Acknowledge (ACK) or a No Acknowledge (NACK) response bit during a ninth bit window. There are no unused clock cycles during any read or write operation, so there must not be any interruptions or breaks in the data stream during each data byte transfer and ACK or NACK clock cycle.

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Single Wire Bus Transactions

Types of data transmitted over the SI/O line:

• Reset and Discovery Response
• Logic ‘0’ or Acknowledge (ACK)
• Logic ‘1’ or No Acknowledge (NACK)
• Start Condition
• Stop Condition

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Resetting the Client

A Reset and Discovery Response sequence is used by the Host to reset the device as well as to perform a general bus call to determine if any devices are present on the bus.

To begin the Reset portion of the sequence, the Host must drive SI/O low for a minimum time. If the device is not currently busy with other operations, the Host can drive SI/O low for a time of t_RESET. The length of t_RESET can vary for different Client modes. Refer to the product datasheet for more information.  

However, if the device is busy, the Host must drive SI/O for a time of t_DSCHG to ensure the device is reset as discussed in the "Interrupting the Device During an Active Operation" section. The Reset time forces any internal charge storage within the device to be consumed, causing the device to lose all remaining standby power available internally.

Upon SI/O being released for a sufficient amount of time to allow the device time to power-up and initialize, the Host must then always request a Discovery Response Acknowledge from the Client prior to any commands being sent to the device. The Host can then determine if a Client is present by sampling for the Discovery Response Acknowledge from the device.

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Device Response Upon Reset or Power-Up

After the Client device has been powered up or after the Host has reset the device by holding the SI/O line low for t_RESET or t_DSCHG, the Host must then release the line which will be pulled high by an external pull-up resistor. The Host must then wait an additional minimum time of t_RRT before the Host can request a Discovery Response Acknowledge from the device.

The Discovery Response Acknowledge sequence begins by the Host driving the SI/O line low which will start the Client’s internal timing circuits. The Host must continue to drive the line low for t_DRR.

During the t_DRR time, the Client will respond by concurrently driving SI/O low. The device will continue to drive SI/O low for a total time of t_DACK. The Host should sample the state of the SI/O line at t_MSDR past the initiation of t_DRR. By definition, the t_DACK minimum is longer than the t_MSDR maximum time, thereby ensuring the Host can always correctly sample the SI/O for a level less than V_IL. After the t_DACK time has elapsed, the Client will release SI/O which will then be pulled high by the external pull‑up resistor.

The Host must then wait t_HTSS to create a Start condition before continuing with the first command (see Start/Stop Condition for more details about Start conditions). By default, the device will come out of Reset.

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Interrupting the Device During an Active Operation

Data Input and Output Bit Frames

Communication is conducted in time intervals referred to as a bit frame and lasts t_BIT in duration. Each bit frame contains a single binary data value. Input bit frames are used to transmit data from the Host to the Client and can either be a logic ‘0’ or a logic ‘1’. An output bit frame carries data from the Client to the Host. In all input and output cases, the Host initiates the bit frame by driving the SI/O line low. Once the Client detects the SI/O being driven below the V_IL level, its internal timing circuits begin to run. The duration of each bit frame is allowed to vary from bit to bit as long as the variation does not cause the t_BIT length to exceed the specified minimum and maximum values. The t_BIT requirements will vary depending on whether the device is set for Standard Speed or High-Speed mode. For more information about setting the speed of the device, refer to the product datasheet.

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Data Input Bit Frames

A data input bit frame can be used by the Host to transmit either a logic ‘0’ or logic ‘1’ data bit to the Client. The input bit frame is initiated when the Host drives the SI/O line low. The length of time that the SI/O line is held low will dictate whether the Host is transmitting a logic ‘0’ or a logic ‘1’ for that bit frame. For a logic ‘0’ input, the length of time that the SI/O line must be held low is defined as t_LOW0. Similarly, for a logic ‘1’ input, the length of time that the SI/O line must be held low is defined as t_LOW1. The Client will sample the state of the SI/O line after the maximum t_LOW1 but prior to the minimum t_LOW0 after SI/O was driven below the V_ILthreshold to determine if the data input is a logic ‘0’ or a logic ‘1’. If the Host is still driving the line low at the sample time, the Client will decode that bit frame as a logic ‘0’ as SI/O will be at a voltage less than V_IL. If the Host has already released the SI/O line, the Client will see a voltage level greater than or equal to V_IH because of the external pull-up resistor, and that bit frame will be decoded as a logic ‘1’. The timing requirements for these parameters can be found in the respective product datasheet. A logic ‘0’ condition has multiple uses in the I²C emulation sequences. It is used to signify a ‘0’ data bit, and it is also used for an Acknowledge (ACK) response. Additionally, a logic ‘1’ condition is also is used for a No Acknowledge (NACK) response in addition to the nominal ‘1‘ data bit. The accompanying figures depict the logic ‘0’ and logic ‘1’ input bit frames. 

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Start/Stop Condition

All transactions to the Client begin with a Start condition; therefore, a Start can only be transmitted by the Host to the Client. Likewise, all transactions are terminated with a Stop condition and thus a Stop condition can only be transmitted by the Host to the Client. The Start and Stop conditions require identical biasing of the SI/O line. The Start/Stop condition is created by holding the SI/O line at a voltage of V_PUP for a duration of t_HTSS. Refer to the applicable product datasheet for timing minimums and maximums.

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Communication Interruptions

In the event that a protocol sequence is interrupted midstream, this sequence can be resumed at the point of interruption if the elapsed time of inactivity (where SI/O is idle) is less than the maximum t_BIT time. The maximum allowed value may differ depending on the Client speed mode.

For systems that cannot accurately monitor the location of interrupts, it is recommended to ensure that a minimum interruption time be observed consistent with the longest busy operation of the device (tWR). Communicating with the device while it is in an internal write cycle by the host driving SI/O low could cause the byte(s) being written to become corrupted and must be avoided. The behavior of the device during a write cycle is described in more detail in Device Behavior During Internal Write Cycle.

If the sequence is interrupted for longer than the maximum t_BIT, the host must wait at least the minimum t_HTSS before continuing. By waiting the minimum t_HTSS time, a new Start condition is created and the device is ready to receive a new command. It is recommended that the host start over and repeat the transaction that was interrupted midstream.

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Data Output Bit Frame

A data output bit frame is used when the Host is to receive communication back from the Client. Data output bit frames are used when reading any data out as well as any ACK or NACK responses from the device. Just as in the input bit frame, the Host initiates the sequence by driving the SI/O line below the V_ILthreshold which engages the Client internal timing generation circuit.

Within the output bit frame is the critical timing parameter t_RD, which is defined as the amount of time the Host must continue to drive the SI/O line low after crossing the below V_IL threshold to request a data bit back from the Client. Once the t_RD duration has expired, the Host must release the SI/O line.

If the Client is responding with a logic ‘0’ (for either a ‘0’ data bit or an ACK response), it will begin to pull the SI/O line low concurrently during the t_RD window and continue to hold it low for a duration of t_HLD0, after which it will release the line to be pulled back up to V_PUP. Thus, when the Host samples SI/O within the t_MRS window, it will see a voltage less than V_ILand decode this event as a logic ’0’. By definition, the t_HLD0time is longer than the t_MRS time and therefore, the Host is ensured to sample while the Client is still driving the SI/O line low.

If the Client intends to respond with a logic ‘1’ (for either a ‘1’ data bit or a NACK response), it will not drive the SI/O line low at all. Once the Host releases the SI/O line after the Client Device Operation and Communication maximum t_RD has elapsed, the line will be pulled up to V_PUP. Thus, when the Host samples the SI/O line within the t_MRS window, it will detect a voltage greater than V_IH and decode this event as a logic ‘1’. The data output bit frame is shown in greater detail:

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Device Addressing

Accessing the device requires a Start condition followed by an 8-bit device address byte. The single-wire protocol sequence emulates what would be required for a I²C Client, with the exception that the beginning four bits of the device address are typically used as an opcode for the different commands and actions that the device can perform (refer to product datasheet for available opcodes). Since multiple Client devices can reside on the bus, each Client device must have its own unique address so that the Host can access each device independently. After the 4-bit opcode, the following three bits of the device address byte are comprised of the Client address bits. The three Client address bits are typically preprogrammed prior to shipment. Obtaining devices with different Client address bit values may require purchasing a specific ordering code. Refer to the applicable product datasheet Packaging Information for explanation of which ordering code corresponds with a specific Client address value.

Following the three Client address bits is a Read/Write select bit where a logic ‘1’ indicates a read and a logic ‘0’ indicates a write. Upon the successful comparison of the device address byte, the Client will return an ACK (logic ‘0’). If the 4-bit opcode is invalid or the three bits of Client address do not match what is preprogrammed in the device, the device will not respond on the SI/O line and will return to a Standby state.

Device Address Byte Format:

Following the device address byte, a memory address byte must be transmitted to the device immediately. The memory address byte contains a memory array address to specify which location in the Client to start reading or writing.

Memory Address Byte Format:

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Write Operations

All write operations to the Client begin with the host sending a Start condition, followed by a device address byte with the R/W bit set to ‘0’ followed by the memory address byte. Next, the data value(s) to be written to the device are sent. Data values must be sent in 8-bit increments to the device followed by a Stop condition. If a Stop condition is sent somewhere other than at the byte boundary, the current write operation will be aborted. Many Client memory devices permit single byte writes, partial page writes, and full page writes. See the product datasheet for details.

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Byte Write

The Host supports writing of a single 8-bit byte and requires a memory word address to select which byte to write.

Upon receipt of the proper device address byte (typically with an opcode, 0xA in this case) and memory address byte, the Client will send a logic ‘0’ to signify an ACK. The device will then be ready to receive the data byte. Following receipt of the complete 8-bit data byte, the Client will respond with an ACK. A Stop condition must then occur; however, since a Stop condition is defined as a null bit frame with SI/O pulled high, the Host does not need to drive the SI/O line to accomplish this. If a Stop condition is sent at any other time, the write operation is aborted. After the Stop condition is complete, the Client will enter an internally self-timed write cycle, which will complete within a time of tWR, while the data is being programmed into the nonvolatile Client. The SI/O pin must be pulled high via the external pull-up resistor during the entire tWR cycle. Thus, in a multi-client environment, communication to other single-wire devices on the bus should not be attempted while any devices are in an internal write cycle. After the maximum tWR time has elapsed, the Host may begin a new bus transaction.

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Device Behavior During Internal Write Cycle

To ensure that the address and data sent to the device for writing are not corrupted while any type of internal write operation is in progress, commands sent to the device are blocked from being recognized until the internal operation is completed. If a write interruption occurs (SI/O pulsed low) and is small enough to not deplete the internal power storage, the device will NACK signaling that the operation is in progress. If an interruption is longer than t_DSCHG then internal write operation will be terminated and may result in data corruption.

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Read Operations

Read operations are initiated in a similar way as write operations with the exception that the Read/Write select bit in the device address byte must be set to a logic ‘1’. There are typically multiple read operations supported by Client devices. In this lesson, we’ll cover the more common types:

• Current Address Read
• Random Read
• Sequential Read

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Current Address Read

The internal Address Pointer must be pointing to a memory location within the Client in order to perform a current address read from the Client. To initiate the operation, the Host must send a Start condition, followed by the device address byte with the opcode (0xA in this case) specified, along with the appropriate Client address combination and the Read/Write bit set to a logic ‘1’. After the device address byte has been sent, the Client will return an ACK (logic ‘0’).

Following the ACK, the device is ready to output one byte (eight bits) of data. The Host initiates all bits of data by driving the SI/O line low to start. The Client will hold the line low after the Host releases it to indicate a logic ‘0’. If the data is logic ‘1’, the Client will not hold the SI/O line low at all, causing it to be pulled high by the pull-up resistor once the Host releases it. This sequence repeats for eight bits.

After the Host has read the first data byte and no further data is desired, the Host must return a NACK (logic ‘1’) response to end the read operation and return the device to the Standby mode. The accompanying figure depicts this sequence.

If the Host would like the subsequent byte, it would return an ACK (logic ‘0’) and the device will be ready to output the next byte in the memory array. Refer to Sequential Read for details about continuing to read beyond one byte.

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Random Read

A random read begins in the same way as a byte write operation which will load a new Client memory address into the Address Pointer. However, instead of sending the data byte and Stop condition of the byte write, a repeated Start condition is sent to the device. This sequence is referred to as a “dummy write”. After the device address and memory address bytes of the “dummy write” have been sent, the Client will return an ACK response. The Host can then initiate a current address read, beginning with a new Start condition, to read data from the Client. Refer to the accompanying figure for details on how to perform a current address read.

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Sequential Read

Sequential reads start as either a current address read or as a random read. However, instead of the Host sending a NACK (logic ‘1’) response to end a read operation after a single byte of data has been read, the Host sends an ACK (logic ‘0’) to instruct the Client to output another byte of data. As long as the device receives an ACK from the Host after each byte of data has been output, it will continue to increment the address counter and output the next byte data from the Client. If the end of the Client is reached, then the Address Pointer will “roll over” back to the beginning (address 00h) of the Client region. To end the sequential read operation, the Host must send a NACK response after the device has output a complete byte of data. After the device receives the NACK, it will end the read operation and return to Standby mode.

Sequential Read from a Current Address Read Waveform:

Sequential Read from a Random Read Waveform:

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