Device Configuration Registers
All Microchip microcontrollers use nonvolatile configuration registers that define basic device behavior. These registers reside in Flash and can only be programmed when the device is programmed. Some of these settings can also be changed during run time. Please see the device data sheet for details.
Here are some examples of the basic behavior determined by these registers:
- Device clock source selection
- Device clock configuration
- PLL configuration
- Watchdog timer enable/disable
- Code protect on
PIC32MX Configuration Registers
This list shows all the device configuration registers for the PIC32MX devices. The purpose of this list is to help you understand what these registers control. Please see the device data sheet (Special Features section) for details.
| Register | Bits found in register |
|---|---|
| Device Configuration Word0 (DEVCFG0) | Code-Protect bit Boot Flash Write-Protect bit Program Flash Write-Protect bits In-Circuit Emulator/Debugger Communication Channel Select bit Background Debugger Enable bits |
| Device Configuration Word1 (DEVCFG1) | Watchdog Timer Enable bit Watchdog Timer Postscale Select bits Clock Switching and Monitor Selection Configuration bits Peripheral Bus Clock Divisor Default Value bits CLKO Enable Configuration bit Primary Oscillator Configuration bits Internal External Switchover bit Secondary Oscillator Enable bit Oscillator Selection bits |
| Device Configuration Word2 (DEVCFG2) | PLL Output Divider bits USB PLL Enable bit USB PLL Input Divider bits PLL Multiplier bits PLL Input Divider bits |
| Device Configuration Word3 (DEVCFG3) | USB VBUSON Selection bit USB USBID Selection bit CAN I/O Pin Selection bit Ethernet I/O Pin Selection bit Ethernet MII Enable bit Shadow Register Interrupt Priority Select bits 16-bit user-defined USERID bit readable via ICSP™ and JTAG |
| Device ID and Revision ID Register (DEVID) | Revision Identifier bits Device ID bits |
PIC32MZ Configuration Registers
A PIC32 family device includes several nonvolatile (programmable) Configuration Words that define device behavior. The device configuration features may vary according to PIC32 family variants; however, the following features are common to all PIC32 devices:
- System Clock Oscillator mode and Phase-Locked Loop (PLL)
- Secondary Oscillator (SOSC) enable/disable
- Watchdog Timer (WDT) enable/disable and postscaler
- Boot Flash and Program Flash write-protect regions
- User ID
- Debug mode
The PIC32 Configuration Words are located in Boot Flash memory and are programmed when the PIC32 Boot Flash region is programmed.
System Clock oscillator and PLL bits provide a large selection of flexible clock source options and PLL prescalers/postscalers.
The SOSC bit enables or disables a low-power SOSC that can serve as a clock source for several peripherals, such as RTCC, Timer1, and CPU.
The WDT and postscaler bits allow the user to permanently disable or enable the WDT. When enabled, a postscaler can be selected to provide a wide range of WDT periods. A Windowed mode watchdog feature is also available.
The Boot Flash and Program Flash write-protected bits provide write protection to all of Boot Flash memory and selected regions of Program Flash memory.
User ID bits are available for programming application-specific or product-specific identification information, such as product ID or serial numbers. Debug mode bits provide a selection of debugging modes and channels.
The following list shows all the device configuration registers for the PIC32MZ devices. The purpose of this list is to help you understand what these registers control. Please see the device datasheet (Special Features section) for details.
| Device Configuration Register | Bits Found in Register |
|---|---|
| Device Code Protect Register (DEVCP0/ADEVCP0) | Code Protect bit |
| Device Configuration Word0 (DEVCFG0/ADEVCFG0) | EJTAG boot enable Debug mode CPU Access Permission bits Flash Sleep mode bit Dynamic Flash ECC Configuration bits Boot ISA Selection bit (MIPS32® or microMIPSTM) Trace Enable bit In-Circuit Emulator/Debugger Communication Channel Select bits JTAG Enable bit Background Debugger Enable bits |
| Device Configuration Word1 (DEVCFG1/ADEVCFG1) | Deadman Timer enable bit Deadman Timer Count Select bits Watchdog Timer Window Size bits Watchdog Timer Enable bit Watchdog Timer Window Enable bit Watchdog Timer Stop During Flash Programming bit Watchdog Timer Postscale Select bits Clock Switching and Monitoring Selection Configuration bits Primary Oscillator Output pin (CLKO) Enable Configuration bit Primary Oscillator Configuration bits Internal External Switchover bit (for two-speed start-up) Secondary Oscillator Enable bit Deadman Timer Count Window Interval bits Oscillator Selection bits |
| Device Configuration Word2 (DEVCFG2/ADEVCFG2) | USB PLL Enable bit USB PLL Input Frequency Select bit Default System PLL Output Divisor bits System PLL Feedback Divider bits System PLL Input Clock Select bit System PLL Divided Input Clock Frequency Range bits PLL Input Divider bits |
| Device Configuration Word3 (DEVCFG3/ADEVCFG3) | USB USBID Selection bit Peripheral Pin Select Configuration bit (IOL1WAY) Peripheral Module Disable Configuration bit Permission Group Lock One Way Configuration bit Ethernet I/O Pin Selection Configuration bit Ethernet MII Enable Configuration bit 16-bit user-defined USERID bit readable via ICSP™ and JTAG |
| Configuration Control register (CFGCON) | DMA Read and DMA Write Arbitration Priority to SRAM bit CPU Arbitration Priority to SRAM When Servicing an Interrupt bit Input Capture Alternate Clock Selection bit Output Compare Alternate Clock Selection bit Peripheral Pin Select Lock bit Peripheral Module Disable bit Permission Group Lock bit USB Suspend Sleep Enable bit Flash ECC Configuration bits JTAG Port Enable bit Trace Output Enable bit TDO Enable for 2-Wire JTAG |
| External Bus Interface Address Pin Configuration register (CFGEBIA) | EBI Pin Enable bit EBI Address Pin Enable bits |
| External Bus Interface Control Pin Configuration register (CFGEBIC) | EBIRDY3 Inversion Control bit EBIRDY2 Inversion Control bit EBIRDY1 Inversion Control bit EBIRDY3 Pin Enable bit EBIRDY2 Pin Enable bit EBIRDY1 Pin Enable bit EBIRDYx Pin Sensitivity Control bit EBIRP Pin Sensitivity Control bit EBIWE Pin Enable bit EBIOE Pin Enable bit EBIBS1 Pin Enable bit EBIBS0 Pin Enable bit EBICS3 Pin Enable bit EBICS2 Pin Enable bit EBICS1 Pin Enable bit EBICS0 Pin Enable bit EBI Data Upper Byte Pin Enable bit EBI Data Lower Byte Pin Enable bit |
| Permission Group Configuration register (CFGPG) | Crypto Engine Permission Group bits Flash Control Permission Group bits SQI Module Permission Group bits Ethernet Module Permission Group bits CAN2 Module Permission Group bits CAN1 Module Permission Group bits USB Module Permission Group bits DMA Module Permission Group bits DMA Module Permission Group bits |
| Device ID and Revision ID register (DEVID) | Revision Identifier bits Device ID bits |
| Device ADC Calibration register (DEVADCx) | Calibration bits for the ADCs |
| Device Serial Number register (DEVSNx) | Device Unique Serial Number bits |