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MIPS32® M4K® CPU Core ISA Overview

Last modified by Microchip on 2023/11/09 09:00

The Instruction Set Architecture (ISA) of a Central Processing Unit (CPU) refers to the lowest-level interface between the programmer and the CPU, and includes the following aspects:

  • Datatypes
    • Supported operand representations
  • Operations on data
    • Arithmetic or other operations that can be performed on the operands
  • Instruction format
  • Memory organization
  • Addressing modes

​ISAs are also often referred to as the "Programmers Model" of a CPU.

PIC32MX, with the MIPS32® M4K® CPU core, implements Release 2 of the MIPS32 architecture in a five-stage pipeline. It includes the MIPS16e™ Application-Specific Extension (ASE), which improves code density by using 16-bit encodings of MIPS32 instructions and some MIPS16e-specific instructions.

This ISA may be classified as a load/store or register-register type (i.e., ALU operations act on register operands only, with no memory references). On modern CPUs, this is done to decouple CPU speed from the main memory speed.

Refer to the "MIPS® Architecture For Programmers Volume I-A: Introduction to the MIPS32® Architecture" for more information on the CPU Programming Model for the MIPS32® core.