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PIC32MZ CPU Overview

Last modified by Microchip on 2023/11/09 09:01

Depending on the device sub-family, PIC32MZ devices are complex System-on-Chip (SoC), which are based on the microAptiv™ microprocessor core or the M-Class M5150 microprocessor core from Imagination Technologies Ltd.

The microAptiv microprocessor core is a superset of the MIPS® M14KE™ and M14KEc™ microprocessor cores. These cores are state-of-the-art, 32-bit, low-power, RISC processor cores with the enhanced MIPS32® Release 2 Instruction Set Architecture (ISA).

The M5150 microprocessor core is a superset of the microAptiv™ microprocessor core. This 32-bit, low-power, RISC processor core uses the enhanced MIPS32® Release 5 Instruction Set Architecture (ISA).

microAptiv MPU core architecture diagram

MIPS32 microAptiv MPU core

The MIPS32 microAptiv MPU core implements the MIPS Release 2 Architecture in a five-stage pipeline. It includes support for the microMIPS™ ISA, with optimized MIPS32 16- and 32-bit instructions that provide a significant reduction in code size with a performance equivalent to MIPS32. The microAptiv MCU/MPU core is an enhancement of the M14Kc core, designed from the same microarchitecture, including the Microcontroller Application-Specific Extension (MCU ASE), enhanced interrupt handling, lower interrupt latency, and nativeAMBA®-3 AHB-Lite Bus Interface Unit (BIU), with additional power saving, debug, and profiling features.

The following key features are available on PIC32 MCUs based on this core:

  • microMIPS variable-length instruction mode for compact code
  • Vectored interrupt controller with up to 256 interrupt sources
  • Atomic bit manipulations on peripheral registers (single cycle)
  • High-speed Microchip ICD port with hardware-based, non-intrusive data monitoring and application data streaming functions
  • EJTAG debug port allows extensive third-party debug, programming, and test tools support
  • Instruction controlled power management modes
  • Five-stage pipeline instruction execution
  • Internal-code protection to help protect intellectual property
  • Arithmetic saturation and overflow handling support
  • Zero-cycle overhead saturation and rounding operations
  • Atomic read-modify-write memory-to-memory instructions
  • MAC instructions with up to four accumulators
  • Native fractional data type (Q15, Q31) with rounding support
  • MIPS Digital Signal Processing (DSP) Application-Specific Extension (ASE) Revision 2, which adds DSP capabilities with support for powerful data processing operations
  • MIPS MCU ASE, which adds enhancements in the areas of interrupt delivery and latency
  • Multiply/Divide unit with a maximum issue rate of one 32 x 32 multiply per clock

MIPS32 M5150 MPU core

The MIPS32 M5150 MPU core implements the MIPS Release 5 Architecture in a five-stage pipeline. In addition to the features described for devices with the microAptiv core, the following key features are common to all PIC32 devices that are based on the M-Class M5150 microprocessor core:

  • Implement the latest MIPS Release 5 Architecture, which includes IP protection and reliability for industrial controllers, Internet of Things (IoT), wearables, wireless communications, automotive, and storage
  • IEEE-754 Single/Double Precision Floating Point Unit (FPU)

​ASE: An application-specific extension to the MIPS architecture. These are optional extensions defined in add-ons to the MIPS32/MIPS64 base architecture. Refer to sections 50.14 and 50.15 in the "Section 50. CPU for Devices with MIPS32 microAptiv and M-Class Cores" of the reference manual for details on these ASEs.

​CPU Core Documentation:
The following documents are available from MIPs: