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Virtual vs Physical Memory

Last modified by Microchip on 2023/11/09 09:01

In all PIC32 architectures, CPU access to memory and peripherals is accomplished through virtual address space. The virtual address space has been segmented to provide the core with flexibility in how it accesses physical memory.

When the CPU is in Kernel mode (default after reset and during exceptions) there are two segments used to access internal memory:

  • KSEG0: Internal memory access - cacheable
  • KSEG1: Internal memory access - not cacheable

KSEG0 and KSEG1 share the same physical addresses and use Fixed Mapping Translation (FMT) to translate virtual to physical addresses. Every virtual address has its own constant corresponding physical address.

Your application can choose to use cache or not based on the segment used to address physical memory.

KSEG0 and KSEG1 share the same physical addresses

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CPU virtual addresses

DMA and peripherals use physical address

KSEG0 is cacheable and KSEG1 is not cacheable

Warning

KSEG1 is the only memory region that can be used at reset because the MMU and cache must be configured by the boot code before it can be used. Therefore your boot code must be placed in KSEG1.

There are two segments used to access external (SQI and EBI) memory:

  • KSEG2: External memory access - cacheable
  • KSEG3: External memory access - not cacheable

There is one segment used to access User (unprivileged) memory:

  • KUSEG: User (unprivileged) memory access - cacheable

KUSEG, KSEG2 and KSEG3 use a Memory Management Unit (MMU) with Translation Lookaside Buffer (TLB) to translate virtual to physical addresses. The MMU must be configured by your boot code before using these segments.

Virtual Physical Memory