Arm® Cortex®-M0+ Sleep Modes

The Arm^® Cortex^®-M0+ core has three Sleep modes to reduce power consumption.

• Normal Sleep
• Deep Sleep (Wake up Interrupt Controller (WIC))
  • The WIC allows an interrupt to be detected even though the clock to the core is disabled.
• Deep Sleep with State Retention Power Gating (SRPG) support (WIC + SRPG)
  • SRPG allows power to be removed from some parts of the core. This helps to reduce the power consumed by transistor leakage.

Power consumption draws for each mode:

• Active mode: Leakage + dynamics
• Sleep mode: Leakage + some dynamics
• Deep Sleep: Leakage
• Deep Sleep with SRPG: State retention only