SAM D21 SERCOM SPI Master Overview
The SAM D21 family of devices include up to six instances of the SERCOM serial communication interface peripheral, which among other things, can be configured to be an SPI Interface.
A SERCOM instance can be configured to be either an SPI Master or an SPI Slave. Both master and slave have an interface containing a shift register, a transmit buffer, and two receive buffers. In addition, the SPI Master uses the SERCOM baud rate generator, while the SPI Slave uses the SERCOM address match logic.
This page focuses on the Master mode of the SERCOM SPI peripheral. Some of the key features of the Master mode SPI operation are:
- Full-duplex, four-wire interface (MISO, MOSI, SCK, SS)
- Single-buffered transmitter, double-buffered receiver
- Supports all four SPI modes of operation
- Single data direction operation allows alternate function on MISO or MOSI pin
- Selectable LSB- or MSB-first data transfer
- Can be used with DMA
- Master operation:
- Serial clock speed up to half the system clock
- 8-bit clock generator
- Hardware controlled SS
The SPI is a four-wire high-speed synchronous data transfer interface. As master, the SPI initiates and controls all data transactions. The four communication lines identified in the diagram below are Slave/Chip Select (CS), Master-In-Slave-Out (MISO), Master-Out-Slave-In (MOSI) and Serial Clock (SCK). There are several ways to designate the communication lines used in and SPI connection. For instance, the figure below is taken from a Microchip Technology Inc. EEPROM data sheet and uses CS, SI and SO while the SAM D21 uses SS, MOSI and MISO respectively to designate chip select, master serial data out, and master serial data in lines.
A typical communication transaction is shown below. The master drives the CS Low, the instruction is clocked from the master on the MOSI (SI) line, and data is clocked back to the master on the MISO (SO) line. The Clock line (SCK) is driven by the master.
