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Learn About the SAM E51 DMAC

Walk-Through SAME51 Direct Memory Access Controller (DMAC) Transfer Descriptors

Last modified by Microchip on 2026/07/08 15:56
   Learn How SAME51 Direct Memory Access Controller (DMAC) Transfer Controls Work  Review SAME51 Direct Memory Access Controller (DMAC) Arbitration   

Introduction

The Direct Memory Access Controller (DMAC) in the SAME51 microcontroller family from Microchip Technology allows data to move between memory and peripherals without continuous Central Processing Unit (CPU) involvement. This capability dramatically improves performance, reduces power consumption and frees the CPU to perform higher‑value tasks.

At the heart of the DMAC are transfer descriptors—small data structures stored in Static Random-Access Memory (SRAM) that tell the hardware what to transfer, where to transfer it and how to proceed afterward. This lesson explains transfer descriptors and linked descriptors from first principles.

The Role of Transfer Descriptors

A transfer descriptor is a 128‑bit (16‑byte) structure that fully defines a single block transfer, where a block is a group of one or more beats (individual bus accesses of 8, 16, or 32 bits). Together with the DMA channel configuration, descriptors determine exactly how the DMAC executes a transfer.

Before a DMA channel can be enabled by setting CHCTRLA.ENABLE = 1 and before it can respond to any trigger, its first transfer descriptor must already be initialized and marked valid by setting BTCTRL.VALID = 1. This first descriptor describes the first block in a DMA transaction. A transaction may consist of one block or many blocks chained together.

All transfer descriptors must reside in SRAM. The DMAC does not fetch descriptors from Flash memory.

Descriptor Memory and Write‑Back Memory

The DMAC uses two SRAM regions whose base addresses are provided by software:

  • Descriptor Memory Section Base Address (BASEADDR): Points to the first transfer descriptor for DMA channel 0
  • Write‑Back Memory Section Base Address (WRBADDR): Points to the write‑back descriptor for DMA channel 0

Because BASEADDR and WRBADDR point only to channel 0, the descriptors for all enabled channels must be placed contiguously in memory and ordered by channel number. For example, the first descriptor for channel 1 must immediately follow the first descriptor for channel 0.

The descriptor memory section contains the initial descriptors for each channel. The write‑back memory section is where the DMAC stores the updated descriptors for channels that are actively transferring data. These write‑back descriptors reflect the current state of an ongoing block transfer, such as the remaining transfer count.

The required size of each section depends on the highest‑numbered enabled DMA channel, denoted as m:

Size = 128bits ⋅ (m + 1)

To conserve SRAM, we recommend using the lowest‑numbered channels whenever possible.

The descriptor and write‑back sections may share the same memory region (BASEADDR = WRBADDR), but we recommend keeping them separate. Using separate regions reduces latency before the first beat is transferred and allows the same transaction to be restarted without rewriting the initial descriptor.

Transfer Descriptor Structure in Memory

SAME51 Direct Memory Access Controller (DMAC) Transfer Descriptor Memory Structure

Each transfer descriptor occupies exactly 128 bits and is laid out in increasing memory addresses as follows:

  • Next Descriptor Address (DESCADDR, 32 bits): Pointer to the next descriptor in a linked list, or zero if this is the last block
  • Destination Address (DSTADDR, 32 bits): Address of the last destination beat in the block
  • Source Address (SRCADDR, 32 bits): Address of the last source beat in the block
  • Block Transfer Count (BTCNT, 16 bits): Specifies how many beats are transferred in this block
  • Block Transfer Control (BTCTRL, 16 bits): Defines beat size, address increment behavior, block completion action, event generation, and descriptor validity

When a block transfer completes and DESCADDR is zero, the DMA channel either suspends or disables itself depending on the Block Action (BLOCKACT) field in BTCTRL. If this descriptor is the last in a linked sequence, the channel is disabled.

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Practical Code Example

The following example shows a C structure that matches the SAME51 transfer descriptor layout and demonstrates how separate descriptors are allocated for the initial and write‑back sections:

typedef struct
{
   uint16_t __attribute__((packed)) CHANNEL0_DMA_BLOCK_CONTROL;
   uint16_t __attribute__((packed)) CHANNEL0_DMA_BLOCK_XFER_COUNT;
   uint32_t __attribute__((packed)) CHANNEL0_DMA_SOURCE_ADDRESS;
   uint32_t __attribute__((packed)) CHANNEL0_DMA_DESTINATION_ADDRESS;
   uint32_t __attribute__((packed)) CHANNEL0_DMA_NEXT_DESCRIPTOR_ADDRESS;
} dmaDescriptor;
/* First (initial) descriptor for channel 0 */
dmaDescriptor __attribute__((address(CHANNEL0_DMA_DESCRIPTOR_BASE_ADDR)))
STRUCT_ch0DmaFirstDescriptor;
/* Write-back descriptor for channel 0 */
dmaDescriptor __attribute__((address(CHANNEL0_DMA_WRITE_BACK_BASE_ADDR)))
STRUCT_ch0DmaCallbackDescriptor;

Each DMA channel has one first descriptor and one write‑back descriptor. The DMAC hardware automatically updates the write‑back descriptor as the transfer progresses.

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Linked Descriptors

A linked descriptor is a transfer descriptor whose DESCADDR field points to another descriptor instead of zero. By chaining descriptors together, the DMAC can automatically execute multiple block transfers back‑to‑back without CPU intervention.

This mechanism enables powerful behaviors such as transferring data between different peripherals, switching buffers automatically, or implementing circular buffers for continuous data streaming.

Linked descriptors work as follows: when a block transfer finishes, the DMAC checks DESCADDR. If it is nonzero, the DMAC fetches the next descriptor from SRAM and immediately begins the next block as part of the same transaction. This process repeats until a descriptor with DESCADDR = 0 is reached.

The benefits of linked descriptors are substantial. They minimize interrupt overhead, allow complex transfer sequences to run autonomously and make deterministic, low‑latency data movement possible—an essential feature for real‑time systems.

Descriptors can be managed dynamically in software. New descriptors may be appended at the end of an existing chain, existing descriptors may be modified, or additional descriptors may be inserted between two already‑linked descriptors, as long as the channel is disabled or safely suspended during modification.

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Benefits of Using DMAC Descriptors

Using transfer descriptors and linked descriptors provides several key advantages. CPU load is dramatically reduced because data movement occurs in hardware. Power consumption drops as the CPU can sleep while transfers proceed. System throughput improves due to parallel CPU and DMAC operation. Finally, complex data flows become predictable and scalable, which is critical in communication, signal acquisition, and control applications.

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Microchip Technology Solutions and Tools

Microchip Technology supports SAME51 DMAC development with several solutions. Atmel START can generate initial DMAC configurations and boilerplate code. MPLAB® Harmony v3 and bare‑metal examples demonstrate descriptor‑based DMA for peripherals such as SERCOM (Serial Peripheral Interface (SPI), Inter-Integrated Circuit (I²C), Universal Synchronous and Asynchronous Receiver and Transmitter (USART)), Analog-to-Digital Converter (ADC), and timers. Detailed SAME51 data sheets and application notes provide authoritative guidance on descriptor layout, arbitration, and low‑power operation.

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Summary

Transfer descriptors are the fundamental building blocks of the SAME51 DMAC. Each 128‑bit descriptor precisely defines one block transfer, while BASEADDR and WRBADDR organize descriptors in SRAM for deterministic hardware access. By linking descriptors, developers can construct autonomous, multi‑step DMA transactions that run with minimal CPU involvement. Mastering descriptors unlocks the full performance and efficiency potential of the SAME51 and is a cornerstone skill for high‑quality embedded system design.

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