Skip to Content

SAMA5D2 Series

Last modified by Microchip on 2025/08/04 15:17

SAMA5D2
The SAMA5D2 series is a high-performance, ultra-low power Arm® Cortex®-A5-based processor that runs up to 500 MHz and features the Arm Neon™ SIMD technology engine. It supports multiple memories, including latest-generation technologies such as DDR3, LPDDR3 and QSPI Flash. They include Arm TrustZone® technology, tamper detection, secure data storage, hardware encryption engine, on-the-fly decryption of code stored in external DDR or QSPI memory and a secure bootloader. A rich set of peripherals, user interfaces and robust security features simplify the design for control panels/HMI, secure IoT gateways, connectivity, barcode scanners, printers and POS terminal applications. The low-power features and small packages are ideal for wearables and other battery-operated consumer devices. The SAMA7D6 Series is delivered with a comprehensive development suite that includes a mainline Linux® distribution and Microchip's MPLAB® X IDE and MPLAB Harmony v3 software framework. 

Key Features

  • Powered by an Arm Cortex-A5 core with Arm TrustZone,  Neon Media Processing Engine running up to 500 MHz
  • 128 KB of scrambled internal SRAM
  • One 160 KB internal ROM
    • 64 KB scrambled and maskable ROM embedding bootloader/secure bootloader
    • 96 KB unscrambled, unmaskable ROM for NAND Flash BCH ECC table
  • Low-power modes
    • Ultra-low-power mode with fast wake-up capability
    • Low-power backup mode with 5 KB SRAM and SleepWalking™ features
  • Peripherals - Up to 128 I/Os
    • LCD TFT controller (LCDC) up to 1024x768 or 1280x768 (still image)
      • Four overlays, rotation, post-processing and alpha blending, 24-bit parallel RGB interface
    • Image Sensor Controller (ISC) supporting up to 5 megapixel sensors with a parallel 12-bit interface 
    •  Two Synchronous Serial Controllers (SSC), two Inter-IC Sound Controllers (I2SC), and one Stereo Class D amplifier (CLASSD)
    • One Peripheral Touch Controller (PTC) with up to 8 X-lines and 8 Y-lines (64-channel capacitive touch)
    • One Pulse Density Modulation Interface Controller (PDMIC)
    • One USB device high-speed port (UDPHS) and one USB host high-speed port or two USB host high-speed ports (UHPHS) 
    • One USB host high-speed port with a High-Speed Inter-Chip (HSIC) interface
    • One 10/100 Ethernet MAC (GMAC)
    • Two high-speed memory card hosts
    • Two host/client Serial Peripheral Interfaces (SPI) 
    • Two Quad Serial Peripheral Interfaces (QSPI)
    • Five FLEXCOMs (USART, SPI and TWI)
    • Five UARTs
    • Two host CAN-FD (MCAN)
    • One Analog Comparator Controller (ACC)
    • Two 2-wire interfaces (TWIHS) up to 400 Kb/s supporting the I2C protocol and SMBUS
    • One full-featured 4-channel 16-bit Pulse Width Modulation (PWM) controller
    • Two 3-channel 32-bit Timer/Counters (TC), supporting basic PWM modes
    • One 12-channel, 12-bit, Analog-to-Digital Converter (ADC) with resistive touchscreen capability
  • Safety
    • Zero-power Power-on Reset (POR) cells
    • Main crystal clock failure detector
    • Write-protected registers
    • Integrity Check Monitor (ICM) based on SHA256
    • Memory Management Unit (MMU)
    • Independent watchdog
  • Security
    • Up to eight tamper pins for static or dynamic intrusion detections
    • Environmental monitors on specific versions: temperature, voltage, frequency and active die shield
    • Secure Bootloader
    • On-the-fly AES encryption/decryption on DDR and QSPI memories (AESB)
    • RTC including timestamping on security intrusions
    • Programmable fuse box with 544 fuse bits
    • Hardware cryptography – SHA (SHA1, SHA224, SHA256, SHA384, SHA512)
    • True Random Number Generator (TRNG)
  •  Packages
    • 289-ball LFBGA, 14 mm x 14 mm, 1.4 mm thickness, 0.8 mm pitch
    • 256-ball TFBGA, 8 mm x 8 mm, 1.05 mm thickness, 0.4 mm pitch
    • 196-ball TFBGA, 11 mm x 11 mm, 0.75 mm thickness, 0.75 mm pitch

Back to Top