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SAMA7G5 Series

Last modified by Microchip on 2025/08/11 11:57

SAMA5D2
The SAMA7G5 series is a high-performance, ultra-low power Arm® Cortex®-A7 CPU-based embedded microprocessor (MPU) running up to 1 GHz, with support for multiple memories such as 16-bit DDR2, DDR3, DDR3L, LPDDR2, LPDDR3, octal/quad Serial Peripheral Interface (SPI) and e-MMC® Flash. The SAMA7G5 series integrates complete imaging and audio subsystems with 12-bit parallel and/or MIPI® CSI-2® camera interfaces up to 8 MP, up to four I2S, one Sony®/Philips® Digital Interface (SPDIF) transmitter and receiver and a 4-stereo channel audio sample rate converter. The device also features a large number of connectivity options and offers advanced security functions (secure boot, secure key storage, high-performance crypto accelerators for Advanced Encryption Standard (AES), Secure Hash Algorithm (SHA), Rivest-Shamir-Adleman (RSA), and ECC). The SAMA7G5 series is available in junction temperature ranges up to 125°C and is AEC-Q100 Grade 2 qualified. The SAMA7G5 series is delivered with a comprehensive development suite that includes a mainline Linux® distribution and Microchip's MPLAB® X IDE and MPLAB Harmony v3 software framework. 

Key Features

  • Powered by an Arm Cortex-A7 core with Arm TrustZone®, NEON™ multimedia architecture, running up to 1 GHz
  • 128 KB of internal SRAM and 5 KB of secure backup RAM
  • 80 KB of maskable ROM embedding a secure bootloader (boot on Quad Serial Peripheral Interface (QSPI) NOR, SD, e-MMC), 96 KB ROM for NAND Flash ECC tables, 40 KB ROM for crypto libraries (RSA, ECC, etc.),11 KB internal One-Time-Programmable (OTP) memory
  • Supports up to 16 Gbit 8-bank DDR2/DDR3/DDR3L/LPDDR2/LPDDR3, up to 533 MHz
  • Supports 6-bit static memory controller
  • Supports 8-bit Single-Level Cell (SLC) and Multi-Level CEll (MLC) NAND controller with up to 32-bit error correcting code
  • One 8-bit high-speed memory card host e-MMC 5.1 (HS400), SD3.0 SDR104 mode support
  • Two 4-bit high-speed memory card hosts e-MMC 4.51 (HS200), SD3.01 SDR104 mode support
  • One octal SPI running up to 200 MHz DDR, one QSPI
  • System
    • Power-on Reset (POR) cells, Reset Controller (RSTC), Shutdown Controller (SHDWC), watchdog, Real-Time Clock (RTC) and secure watchdog timers
    • Two internal trimmed RC oscillators with typical values: 32 kHz and 12 MHz
    • Two crystal oscillators: 32.768 kHz and 20 to 50 MHz
    • Eight Phase-Locked Loops (PLLs) for core, system bus and peripherals, serial interfaces, DDR I/Os, pixel clock, audio, USB, MIPI CSI-2 and Ethernet
    • Two 32-channel Direct Memory Access (DMA) with per-channel security configuration
    • One 8-channel DMA dedicated to memory-to-memory transactions  
    • Eight programmable clock output signals
  • Power Considerations
    • Low-power consumption in Backup mode with 5 KB of secure backup SRAM and DDRSDRAM in Self-Refresh mode
    • Low-power with SRAM and register retention, wake-up from various events (USB, CAN, Ethernet WOL, FLEXCOMs), internal events (RTC, timer) and I/O activity
    • Embedded Low Drop-Out (LDO) regulators for MIPI CSI-2, analog and PLLs, to enable low-cost power management solutions
    • Optimum connection to Microchip MCP16501/2 PMICs to enter and exit various power modes of the application
  • Multimedia Peripherals
    • Audio
      • Two synchronous serial controllers, each with 16 channels of up to 32-bit Time Division Multiplexed (TDM) data
      • One inter-IC sound multi-channel controller with TDM256 support
      • Up to two 4-channel pulse density microphone controllers
      • Audio sample rate converter including four stereo channels
    • Image
      • Image sensor controller, ITU-R BT. 601/656
      • 2-lane MIPI CSI-2 (MIPI D-PHY℠) and 12-bit RGB interface support
  • Peripherals
    • Two high-speed USB devices and three high-speed USB hosts sharing three on-chip transceivers
    • One 10/100/1000 Gigabit Ethernet MAC supporting RGMII, MII and RMII (GMAC0) and one 10/100 Ethernet MAC supporting MII and RMII (GMAC1)
    • Six flexible data rate CAN-FD controllers
    • Twelve FLEXCOMs (USART, SPI and TWIHS)
    • Six 64-bit timers
    • Two three-channel 32-bit timer counters with Pulse-Width Modulation
      Pulse-Width Modulator (PWM) generation
    • One four-channel 16-bit PWM controller
    • One 19-channel 12-bit analog-to-digital converter, up to 1 MSPS
  • Safety
    • Temperature and core voltage monitoring
    • Zero-power power-on reset cells
    • Main crystal monitor and clock failure detector with failsafe switchover to main RC oscillator
    • 32 kHz crystal monitor and clock failure detector with failsafe switchover to internal 32 kHz RC oscillator
    • Integrity check monitor based on SHA-256
    • Safety critical modules (Watchdog Timer (WDT), RSTC, SHDWC, etc.) running on always-on slow RC oscillator
    • Register write protection
  • Security
    • Arm TrustZone support
    • One Secure TrustZone watchdog timer running on RC oscillator
    • Secure backup SRAM
    • 256-bit general-purpose backup register, erasable on tamper detection
    • Programmable OTP with bits available for user purposes
    • Configurable JTAG/SWD security
    • 128-bit AES on-the-fly encryption/decryption on DDR memory, SMC, QSPI0 and QSPI1,
    • True random number generator
    • Secure RTC
    • Cryptography – SHA (SHA-1, SHA-224, SHA-256, SHA-384, SHA-512)   
  • Up to 136 I/Os
  • Junction Temperature (TJ ) Range Operating Conditions
    • Industrial TJ: -40°C to +105°C
    • Extended Industrial or Automotive TJ: -40°C to +125°C
  • Qualification: AEC-Q100 Grade 2 qualified (-E/4HBVAO devices only)
  • 343-ball Thin Profile Fine Pitch Ball Grid Array (TFBGA), 14 x 14 x 1.2 mm, 0.65 mm pitch, optimized for standard class Printed Circuit Board (PCB) layout (down to four layers)

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