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megaAVR® Interrupts Overview

Last modified by Microchip on 2023/11/10 11:09

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The megaAVR® family provides several different interrupt sources, all of which are maskable and are divided into three categories:

  • Internal Peripheral Interrupts
    • Associated with Timers, USART, SPI, ADC peripherals
  • External Pin Interrupts
    • Associated with the INT0-INT7 external interrupt pins
  • Pin Change Interrupts
    • Associated with PCINT0-PCINT2 external interrupts occurring on a port pin change

Peripherals are assigned individual interrupt enable bits in their respective interrupt mask register which must be written as a logic one together with the Global Interrupt Enable I-bit in the Status Register in order to enable the interrupt.

AVR Global Interrupt Enable

Reset & Interrupt Vector Locations

The Reset & Interrupt sources each have a separate program vector in the program memory space. The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors as follows:

Vectors

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Vector Relocation

The user can relocate the RESET vector as well as the start location of the Interrupt vectors to the Boot Flash Section of program memory space by programming the BOOTRST fuse bit to 0 and setting the IVSEL bit of the Microcontroller Configuration Register (MCUCR) to 1. The possible RESET and interrupt vector placement are as follows:
 

BOOTRST Fuse

The Boot Reset Address is set by BOOTSZ0/BOOTSZ1 fuse bits as shown in Table 32-7 for ATmega328PB:

bootflash328pb.png

​

To avoid unintentional changes of Interrupt Vector tables, a special write procedure must be followed to change the IVSEL bit:

  • Write the Interrupt Vector Change Enable (IVCE) bit to one.
  • Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.

Here is a code sample showing how to modify the IVSEL bit and relocate the interrupt vectors:

void move_interrupts(void)
{
  uchar temp;
 /* GET MCUCR */
  temp = MCUCR;
 /* Enable change of Interrupt Vectors */
  MCUCR = temp | (1 << IVCE);
 /* Move interrupts to Boot Flash section */
  MCUCR = temp | (1 << IVSEL);
}        

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Priority Level

Each vector has a pre-determined priority level; the lower the address, the higher the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. Table 16-1 depicts the partial vector listing for the ATmega328PB MCU:

AVR Vector Priority

Interrupt Processing

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.

User software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine.

There are basically two types of interrupts, persistent interrupts and non-persistent interrupts.

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Persistent Interrupts

This type of interrupt will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags.

Example: USART Receive Complete Interrupt

The USART contains a Receive Complete Flag (RXC) which is set if there is unread data in the receive buffer. When the Receive Complete Interrupt Enable (RXCIE) in UCSRnB is set, the USART Receive Complete interrupt will be executed as long as the RXC Flag is set (provided that global interrupts are enabled). When interrupt-driven data reception is used, the receive complete routine must read the received data from UDR in order to clear the RXC Flag, otherwise a new interrupt will occur once the interrupt routine terminates.

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Non-Persistent Interrupts

This type of interrupt is triggered by an event that sets an Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority.

Example: Timer/Counter0 Overflow Interrupt

Bit-0 of the Timer0 Interrupt Flag Register (TIFR0) contains the TOV0 interrupt flag. This flag is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed.

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