How to Create a Demultiplexer Circuit
Overview
A demultiplexer (DEMUX) is a device that routes a single input signal to one of several output lines based on selection inputs, leaving unused outputs at 0. It operates as the inverse of a multiplexer (MUX), which combines multiple inputs into a single output. DEMUX is commonly used in communication systems to separate multiplexed signals into individual channels, in digital circuits for decoding addresses and distributing data, and in debugging logic circuits (e.g., WS2812 code with a two-output DEMUX). Using the CLB peripheral, the DEMUX logic can be configured to operate independently of the CPU, streamlining processing.
The demultiplexer uses AND gates and inverters to route the input signal (In) to the correct output based on the selection bits (sel). Each AND gate combines the input signal with specific combinations of inverted and non-inverted selection bits, following the truth table. For example, out0 uses all inverted selection bits, while out1 and out2 have sel0 and sel1 non-inverted, respectively. The diagram shows a four-output configuration.
| Inputs | Outputs | ||||
| Sel0 | Sel1 | Out0 | Out1 | Out2 | Out3 |
| 0 | 0 | In | 0 | 0 | 0 |
| 0 | 1 | 0 | In | 0 | 0 |
| 1 | 0 | 0 | 0 | In | 0 |
| 1 | 1 | 0 | 0 | 0 | In |
Requirements
- Configurable Logic Block (CLB) Peripheral
- Find a Part - Microcontroller and Processor Products Page
Procedure
Implement the CLB Logic
Configure the CLB to implement the demulitplexer logic. Refer to the block diagram for guidance.
Assign the input signal (In) to the appropriate input pin and map the selection inputs (sel) to control pins. Connect each output (out0, out1, etc.) to its designated output pin, ensuring proper routing for the intended functionality.
Verify the Design
Confirm the demultiplexer functionality using a debugging tool to ensure proper operation.
Results
This waveform demonstrates a 1-to-4 demultiplexer (demux) working correctly. The input (In) is routed to one of the four outputs (out0, out1, out2, out3) based on the selection lines (Sel0 and Sel1). For Sel0 and Sel1 combinations (00, 01, 10, 11), the input is directed to out0, out1, out2, and out3, respectively. Only the selected output mirrors the input while others remain low, confirming proper operation.
Learn More
- Code Example: SPI to WS2812 — Use Case for CLB Using the PIC16F13145 Microcontroller with MCC Melody
- CLB Peripheral Page
- More CLB Examples
- Microchip TRY: Live CLB Demonstration
- How to Import External Libraries into Configurable Logic Block Synthesizer Tool
- How to Create a Module in the Configurable Logic Block (CLB) Synthesizer Tool