How to Create a Divide-By-Three Circuit Using MPLAB® Melody
To achieve a divide by three with a duty cycle of 50 percent of an input signal, a common sequential logic implementation is done using three x D-type Flip-Flops (DFF) connected in sequence. The first two DFFs are clocked using a positive edge clock while the last DFF is clocked with a negative edge clock.
The sequential logic in the Configurable Logic Block (CLB) on some devices can only be clocked by a single source without the ability to invert the clock signal. However, many MCUs with CLB peripheral will also feature additional logic peripherals like the Configurable Logic Cell (CLC) which also contain their own DFF. This tip demonstrates how the CLB can be used with two CLCs to implement the divide by three with a 50 percent duty cycle.
Support Files
The MPLAB® X IDE project for this training can be downloaded from GitHub. It is based on the PIC16F13145 Curiosity Nano Demonstration Board.
Requirements
- MPLAB X IDE (includes MPLAB® Code Configurator (MCC) Melody)
- Demonstration board using a Microchip MCU with Configurable Logic Block (CLB) peripheral
- For example, PIC16F13145 Curiosity Nano (EV06M52A)
- Compatible debugger (if demonstration board doesn't provide one)
- Oscilloscope or logic analyzer
Procedure
. Configure CLB to use two DFF cascaded with the output of each inverted and then routed as inputs to a 2-input AND gate whose output is connected to the first DFF input. Clock input to CLB is the signal to be divided and the output of the last DFF connected to an output pin.
Update pin assignments in Pin Grid View pane, as shown:
Results
