8-bit Enhanced Mid-Range PIC16F1xxx Configuration Bits
Configuration Bits are a collection of binary data located in the flash memory of a PIC® microcontroller (MCU). Configuration bits are programmed into the PIC MCU with the application code. They are not executable code as their address is not accessible by the Program Counter (PC). When programmed into a PIC MCU, configuration bits complete circuitry which enables or disables hardware features of the MCU.
Configuration bits are read when exiting a reset and cannot be modified during run-time.
The special features of MCU operation controlled by the configuration bits include:
- System Clocking
- Power Management
- Device Security
- Operating Characteristics
Configuration bits are generated from compiler/assembler directives included in the source code files.
This page describes what features are controlled by configuration bits and how to generate them in the source code.
Location and Format
The configuration bits for the PIC16F1 MCU family are combined into two 14-bit words called CONFIG1 and CONFIG2. The configuration words are located beyond the reach of the PC at addresses 0x8007 and 0x8008 in the MCU's flash memory.
![Register 10-2 CONFIG2 table from the datasheet](/xwiki/bin/download/products/mcu-mpu/8bit-pic/enhanced-family/emconfig/WebHome/config2.png?rev=1.1)
Configuration Settings from PIC16F1937 Datasheet
Configuration bits are inserted into the application's source code. When a PIC MCU project is built, the configuration bit settings are loaded into the HEX output file. The configuration bits are programmed into the PIC with the application program.
Generating Configuration Bits in C Code
Microchip's MPLAB® XC8 C compiler accepts #pragma directives to set the configuration bits.
Sample of Setting Configuration Bits in C
#config pragma FOSC = ECH
#config pragma WDTE = ON
#config pragma PWRTE = OFF
#config pragma MCLRE = ON
#config pragma CP = OFF
#config pragma BOREN = ON
#config pragma CLKOUTEN = OFF
Once written, the compiler directives must be added to the PIC MCU project in one of three ways:
- In a stand-alone C source file which is added to the project
- In a header (.h) file placed in the project with an #include statement
- Placed directly inside one of the source code files already in the project
Generating Configuration Bits in Assembly
When working with Assembly language, the programmer is required to generate the specific 14-bit values for each of the two configuration addresses. Once the patterns are generated the program makes a call to the CONFIG directive to set each of the configuration words.
A 14-bit pattern for each individual configuration bit setting is listed in the .INC file for each PIC MCU. The 14-bit value passed to the CONFIG directive is generated by logically AND-ing the bit settings in the .INC file.
The code to generate and load the configuration bits can be placed in any assembly source file in the project.
System Clocking
Clock Source (FOSC)
FOSC consists of three individual configuration bits: FOSC2,FOSC1, and FOSC0. The FOSC bit-field is located in CONFIG1.
FOSC selects the clock source for MCU.
The options for FOSC are:
FOSC<2:0> | Setting | Clock Soure |
---|---|---|
0 0 0 | INTOSC | Internal Oscillator |
0 0 1 | EXTRC | External RC Oscillator |
0 1 0 | HS | External High Speed Crystal Oscillator |
0 1 1 | XT | External Crystal Oscillator |
1 0 0 | LP | External Low Power Crystal Oscillator |
1 0 1 | ECH | External Clock w/ frequency range 4 - 32 MHz |
1 1 0 | ECM | External Clock w/ frequency range 0.5 - 4 MHz |
1 1 1 | ECL | External Clock w/ frequency range 0 - 0.5 MHz |
Example: Selecting the System Clock
#include <xc.h>
#pragma config FOSC = HS
Fail Safe Clock Monitor (FCMEN)
The FCMEN is a single configuration bit residing in CONFIG1.
FCMEN controls the operation of the Fail-Safe Clock Monitor allowing the clock to switch from external to internal in the event of an external clock failure.
The options for FCMEN are:
FCMEN | Setting | Fail-Safe Clock Monitor Function |
---|---|---|
0 | OFF | Disabled |
1 | ON | Enabled |
Example: Enabling Fail Safe Clock Monitor
include <xc.h>
#pragma config FCMEN = ON // Enable Fail Safe CM
Intlernal/External Switch-over (IESO)
The IESO is a single configuration bit residing in CONFIG1.
IESO sets the mode for clock switching and two-speed start-up. With IESO enabled the clock source can be controlled by the application program.
The options for IESO are:
IESO | Setting | Two Speed Star-up Function |
---|---|---|
0 | OFF | Disabled |
1 | ON | Enabled |
Example: Enabling Two Speed Start-up
#include <xc.h>
#pragma config IESO = ON
Enabling Clock Output (CLKOUTEN)
The CLKOUTEN is a single configuration bit residing in CONFIG1.
CLKOUTEN allows the OSCx/CLCKOUT pin to output the internal system clock. This allows the PIC16F1xxx system clock to drive other components.
The options for CLKOUTEN are:
CLKOUTEN | Setting | CLKOUT function |
---|---|---|
0 | ON | Fosc will be output to OSCx/CLKOUT |
1 | OFF | OSCx/CLKOUT will be the oscillator or a peripheral function |
Example: Outputting the Internal System Clock
#include <xc.h>
#pragma config CLKOUT = ON
Phase Lock Loop Enable (PLLEN)
PLLEN is a single configuration bit residing in CONFIG2.
The internal oscillator's 4 X Phase Lock Loop (PLL) is controlled by a combination of the PLLEN configuration bit and the SPLLEN bit in the OSCON register.
The options for PLLEN are:
PLLEN | Setting | Internal PLL function |
---|---|---|
0 | ON | 4 X PLL is always enabled |
1 | OFF | 4 X PLL is controlled by SPLLEN bit in OSCCON |
Example: Enabling the Internal Phase Lock Loop
#include <xc.h>
#pragma config PLLEN = ON
Power Management
Brown-out Reset Enable (BOREN)
The BOREN configuration setting consists of two individual bits: BOREN1 and BOREN0. The BOREN bit-field resides in CONFIG1.
BOREN allows an MCU RESET to occur if Vdd drops below a preset value. The voltage level precipitating the RESET is determined by the configuration bit BORV.
There are four options for the two BOREN bits:
- Brown-out Reset is always enabled
- Brown-out Reset is always disabled
- Brown-out Reset is enabled when running but disabled when MCU enters SLEEP mode
- Brown-out Reset is controlled at run-time by the SBOREN bit of the PCON register.
BOREN | Setting | Brown-out RESET Function |
---|---|---|
1 1 | ON | Always enabled |
0 0 | OFF | Always disabled |
1 0 | NSLEEP | Enabled while ACTIVE, disabled with in SLEEP mode |
0 1 | SBODEN | controlled by SBOREN bit of PCON Register |
Example: Disabling Brown-out RESET
#include <xc.h>
#pragma config BOREN = OFF
Brown-out Voltage Level (BORV)
BORV is a single configuration bit residing in CONFIG2.
BORV is only applicable when the Brown-out Reset (controlled by the BOREN configuration bit) is active.
BORV selects one of two pre-set voltage levels as the Brown-out Reset voltage.
The voltage levels set by BORV are:
BORV | Setting | Brown-out Voltage |
---|---|---|
0 | L0 | 1.9 volts |
1 | HI | 2.5 volts |
Example: Enable Brown-out RESET to always be active and triggered at 2.5 V.
#include <xc.h>
#pragma config BOREN = ON
#pragma config BORV = HI
Example: Enable Brown-out RESET at 1.9 V while MCU is ACTIVE and disable Brown-out in SLEEP mode.
#include <xc.h>
#pragma config BOREN = NSLEEP
#pragma config BORV = LO
Voltage Regulator (VCAPEN - LDO)
The VCAPEN configuration setting consists of two individual bits: VCAPEN1 and VCAPEN0. The VCAPEN bit-field resides in CONFIG2.
For devices with an internal LDO regulator, VCAPEN determines which pin is assigned as the Vcap pin.
The settings for VCAPEN are:
VCAPEN | Setting | Function |
---|---|---|
0 0 | RA6 | RA6 is assign as Vcap |
0 1 | RA5 | RA5 is assign as Vcap |
1 0 | RA0 | RA0 is assign as Vcap |
1 1 | OFF | Vcap is disconnected from all pins |
Not all PIC16F1xxx MCUs have an internal LDO regulator. Please refer to the datasheet of the PIC MCU you are using to determine if there is an LDO and what pins are available as Vcap.
Example: Assigning Vcap to RA6
#include <xc.h>
#pragma config VCAPEN = RA6
Disabling Vcap functionality
#include <xc.h>
#pragma config VCAPEN = OFF
Low Voltage Programming (LVP)
LVP is a single configuration bit residing in CONFIG2.
Low Voltage programming entry mode allows PIC16F1xxx MCUs to be programmed with only Vdd. Using LVP eliminates the need to supply a higher than Vdd voltage on MCLR/Vpp.
The settings for LVP are:
LVP | Setting | Programming Function |
---|---|---|
1 | ON | Enabled |
0 | OFF | Disabled |
Example: Disabling EEPROM Reads from External Sources
#include <xc.h>
#pragma config LVP = OFF
Device Security
CPD - Data EEPROM Read Protection
CPD is a single configuration bit residing in CONFIG1.
The internal data EEPROM memory can be protected from external reads with CPD . External programmers are prohibited from reading protected EEPROM. The contents of EEPROM is still available for reads from internal sources.
The settings for CPD are:
CPD | Setting | EEPROM Read Protection Function |
---|---|---|
0 | ON | Enabled - EEPROM is not readable |
1 | OFF | Disabled - EEPROM is readable |
Example: Disabling EEPROM Reads from External Sources
#include <xc.h>
#pragma config CPD = ON
Program Memory READ Protection (CP)
CP is a single configuration bit residing in CONFIG1.
The entire program memory space can be protected from external reads with CP .
You will see all 0s when you read protected program memory. The contents of program memory are still available for reads from internal sources.
The settings for CP are:
CP | Setting | Read Protection Function |
---|---|---|
0 | ON | Enabled - memory is not readable |
1 | OFF | Disabled - memory is readable |
Example: Disabling External Program Memory Reads
#include <xc.h>
#pragma config CP = ON
Flash Self Write Enable (WRT)
WRT consists of two individual configuration bits: WRT1 and WRT0. The WRT bit-field is located in CONFIG2.
WRT establishes the address range in which the program memory can be written by the user program.
The settings for WRT are:
WRT | Setting | Flash Self Right Functionality |
---|---|---|
1 1 | ALL | No memory can be written to by user program |
1 0 | BOOT | Address range 0 - 0x1FF write protected 200 h - FFFn write-able |
0 1 | HALF | Address range 0 - 0x7FF write protected 800 h - FFFn write-able |
0 0 | OFF | All memory addresses can be written to by user program |
Operating Characteristics
Pin Control for MCLR (MCLRE)
MCLRE is a single configuration bit residing in CONFIG1.
MCLRE controls the function of the MCLR /Vpp pin.
MCLRE is ignored if the Low Voltage Programming (set by the LVP configuration bit) is not enabled.
The settings for MCRLE are:
MCLRE | Setting | Function |
---|---|---|
1 | ON | Pin function is MCLR /Vpp with internal weak pull-up enabled |
0 | OFF | Pin function is digital input with internal pull-up controlled by WPUx |
Example: Leaving MCRL/Vpp as the RESET pin.
#include <xc.h>
#pragma config MCLRE = ON
Making MCRL/Vpp a digital input pin.
#include <xc.h>
#pragma config MCLRE = OFF
Power-up Timer (PWRTE)
PWRTE is a single configuration bit residing in CONFIG2.
The Power-up Time provides a nominal 72 ms delay after a Power-on Reset or a Brown-out Reset to allow Vdd to stabilize. Enabling or disabling this delay is controlled by PWRTE.
The options for PWRTE are:
PWRTE | Setting | Power-up Timer Function |
---|---|---|
0 | ON | Disabled |
1 | OFF | Enabled |
Example Enabling Power-on Timer
#include <xc.h>
#pragma config PWRTE = ON
Watchdog Timer Enable (WDTE)
The WDTE configuration setting consists of two individual bits: WDTE1 and WDTE0. The WDTE bit-field resides in CONFIG1.
WDTE allows an MCU RESET to occur if the internal Watchdog Timer rolls over from 0xFF to 0x00 before the MCU can execute a CLRWDT instruction.
There are four options for the two WDTE bits:
- Watchdog Timer Reset is always enabled
- Watchdog Timer Reset is always disabled
- Watchdog Timer Reset is enabled when running but disabled when MCU enters SLEEP mode
- Watchdog Timer Reset is controlled at run-time by SWDTEN bit of the WDTCON register
WDTE | Setting | Watch Dog Reset Function |
---|---|---|
1 1 | ON | Always Enabled |
0 0 | OFF | Always Disabled |
1 0 | NSLEEP | Enabled while ACTIVE, Disabled when in SLEEP mode |
0 1 | SBODEN | Controlled by SBOREN bit of PCON Register |
Hardware Stack Overflow (STVREN)
STVREN is a single configuration bit residing in CONFIG2.
The STVREN configuration bit enables or disables a RESET on a stack overflow or underflow.
A stack overflow or underflow always sets the STKOVF or STKUNF bit in the PCON register regardless of STVREN's value.
The options for STVREN are:
STVREN | Setting | Function |
---|---|---|
1 | ON | Stack over/under flow RESET is ENABLED |
0 | OFF | Stack over/under flow RESET is DISABLED |
#pragma config STVREN = ON