Timer2/4/6

The Timer2/4/6 modules are 8-bit timers that incorporate the following features:

• 8-bit Timer and Period registers (TMR2 and PR2)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16, and 1:64)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2 match with PR2
• Optional use as the shift clock for the MSSP module

Some PIC^® MCU devices only have a Timer2. Timer4 and Timer6 are just duplicates of the Timer2 peripheral. By adding more of this type of timer, a device can control multiple PWM outputs from different clock bases.

Timer2 has many features built in but its main feature is the ability to compare its contents to a fixed value stored in a separate register (PR2). When the two values match, then different events can be triggered, such as toggling a PWM pin from a high to low state.

Timer2/4/6 Operation

Timer2 is driven by the internal instruction clock (FOSC/4). The Timer2 (TMR2) register increments on each clock edge. A prescaler on the clock input allows direct input (1:1), divide-by-4, divide-by-16 and on some devices divide-by-64 prescale options. These options are selected by the prescaler control bits: T2CKPS of the Timer2 Control (T2CON) register. The value of TMR2 is compared to that of the Period (PR2) register on each clock cycle. When the two values match, the comparator generates a match signal as the timer output for other peripherals to use as a time base. A Timer2 interrupt can also be triggered by the match. The match signal becomes the input to an optional postscaler and also resets the value of TMR2 to 00h on the next cycle.

The TMR2 and PR2 registers are both directly readable and writable. The TMR2 register is cleared on any device reset, whereas the PR2 register initializes to FFh. Both the prescaler and postscaler counters are cleared on the following events:

• a write to the TMR2 register
• a write to the T2CON register
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• MCLR Reset
• Watchdog Timer (WDT) Reset
• Stack Overflow Reset
• Stack Underflow Reset
• RESET Instruction

Timer2 can be turned on and off via the TMR2ON bit of the T2CON register.

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Timer2/4/6 Interrupts

Timer2 can generate an interrupt when the TMR2 and PR2 registers match. That match signal can also feed a postscaler to delay the number of matches required to initiate a Timer2 interrupt. The output of the postscaler sets the Timer2 Interrupt Flag bit (TMR2IF) of the Peripheral Interrupt (PIR1) register. The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit (TMR2IE) of the Peripheral Interrupt Enable (PIE1) register.

TOUTPS3:TOUTPS0

0000 = 1:1

0001 = 1:2

0010 = 1:3

…

1111 = 1:16

The postscaler has a range of 1:1 through 1:16 and is selected by the Timer Output Postscaler Select bits (T2OUTPS) of the Timer2 Control register (T2CON).

Timer2/4/6 Output Options

The output of the TMR2 match signal is available directly to the CCP modules, where it is typically used as a time base for operations in PWM mode. Having multiple Timer2 style time bases (e.g., Timer4, Timer6) can offer multiple unique PWM signals from a single PIC MCU device.

The TMR2 match signal can also be directed to the Master Synchronous Serial Port (MSSP) to act as the shift clock source when the MSSP is operating in SPI mode.

Timer2/4/6 Sleep Mode

The Timer2 timers cannot be operated while the processor is in Sleep mode. The contents of the TMR2 and PR2 registers will remain unchanged while the processor is in Sleep mode.