dsPIC33A 12-bit 40MSPS Analog-to-Digital Converter (ADC) Deep Dive
Conversion Triggers
| Sampling Modes | Special Features |
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In Analog-to-Digital Converter (ADC) operation, conversion triggers determine when a sampled analog signal is digitized.
Each data channel provides flexible conversion trigger options, depending on the conversion mode and setting of the TRG1SRC[5:0] and TRG2SRC[5:0] bits in the ADnCHxCON1 register.

In this section, we will provide an overview of several primary conversion types and features:
- Triggers Overview
- Software Trigger
- This trigger initiates conversions directly from the application code, allowing precise synchronization with software events.
- Back-to-Back Trigger
- This trigger automatically starts each new conversion as soon as the previous one finishes, making it ideal for rapid, continuous sampling.
- ADC Repeat Timer Trigger
- This trigger generates periodic conversion triggers based on a programmable timer, which is well-suited for regular, time-based sampling requirements.
- Peripheral and Pin Trigger
- This trigger uses signals from external pins or on-chip peripherals (such as PWM, timers, or logic cells) to synchronize conversions with hardware events.
- Trigger Conversion Priority
Triggers Overview
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Two key points are essential to understanding conversion triggers:
- Trigger Source 1 (TRG1SRC[5:0]) initiates the start of the conversion process and is always required.
- Trigger Source 2 (TRG2SRC[5:0] initiates each subsequent conversion in multi-sample modes.
Triggers are always properly synchronized with the core’s free-running, asynchronous conversion clock to ensure accurate data collection.
The following graphic summarizes when/where each trigger source selection field is used:
| TRG1SRC[5:0] | TRG2SRC[5:0] |
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Software Trigger
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- Benefits
- The software trigger allows the user application code to directly initiate ADC conversions, making it easy to synchronize sampling with code execution.
- How to generate a trigger
- To enable software triggering, set Trigger 1 (TRG1SRC[5:0]) to ‘000001’.
- How it works
- The software trigger is generated when the corresponding bit in the ADnSWTRG register is asserted.
- Example code to trigger a conversion on ADC1 and Data Channel 1: AD1SWTRGbits.CH1TRG = 1;
- Software trigger can be used to:
- Start a single sample conversion,
- Begin a multi-sample conversion sequence, and
- Trigger subsequent conversions in multi-sample modes.
- Software triggers can also be used to initiate conversions within a window, but cannot define the window itself in Window mode.
- Trigger timing occurs in the processor clock domain and requires synchronization to the ADC timing domain.
- The software trigger is generated when the corresponding bit in the ADnSWTRG register is asserted.
- Configuration example
- ADnCHxCON1bits.TRG1SRC = 1; // Software trigger for initial conversion
Back-to-Back Trigger
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- Benefits
- The back-to-back trigger enables the accumulation of multiple samples for detailed analysis.
- Conversions continue automatically until the specified sample count is reached.
- How to generate a trigger
- Set Trigger 1 (TRG1SRC[5:0]) to the initial trigger source.
- Set Trigger 2 (TRG2SRC[5:0]) to ‘000010’ to enable back-to-back operation.
- How it works
- Each new conversion starts immediately after the previous one completes, ensuring seamless back-to-back sampling.
- This trigger produces a continuous stream of conversion signals for uninterrupted multi-sample data collection.
- Trigger timing is managed in the ADC clock domain for precise control.
- Configuration example
- ADnCHxCON1bits.TRG1SRC = 1; // Software trigger for initial conversion
- ADnCHxCON1bits.TRG2SRC = 2; // Immediate re-trigger for subsequent conversions
ADC Repeat Timer Trigger
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- Benefits
- The ADC Repeat Timer trigger enables automatic, repeated conversions until the desired count is reached.
- Flexible trigger periods let you customize the conversion rates for your application.
- How to generate a trigger
- Set Trigger 1 (TRG1SRC[5:0]) to the initial trigger source.
- Set Trigger 2 (TRG2SRC[5:0]) to ‘000011’ to enable ADC Repeat Timer operation.
- How it works
- When the internal counter matches the value in RPTCNT[5:0], a trigger event is generated.
- The repeat timer delivers periodic, customizable triggers (adjustable TAD cycles between triggers), ideal for multi-sample operations
- This method ensures fair allocation of ADC bandwidth across all channels. (In between triggers, other channels can be serviced)
- Triggers are generated in the ADC clock domain, minimizing synchronization delays.
- Configuration example
- ADnCHxCON1bits.TRG1SRC = 1; // Software trigger (or other available choices for Trigger 1)
- ADnCHxCON1bits.TRG2SRC = 3; // Conversion Repeat Timer trigger
Peripheral and Pin Trigger
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- Benefits
- Peripheral and pin triggers allow Data Channel conversions to be initiated directly by hardware events.
- This trigger type ensures conversions are precisely synchronized with the active state of the peripheral.
- How to generate a trigger
- Set Trigger 1 (TRG1SRC[5:0]) to any value from ‘000001’ to ‘100111’, and/or Trigger 2 (TRG2SRC[5:0]) to any value from ‘000100’ to ‘100111’ to enable peripherals and pin trigger operation.
- How it works
- Conversions can be triggered by peripherals such as Pulse Width Modulation (PWM), MCCP/SCCP (OCMP/ICAP), Peripheral Trigger Generator (PTG), Integrated Touch Controller (ITC), or Configurable Logic Cell outputs.
- An external pin can also be used as a trigger source.
- This trigger method enables precise synchronization of data conversions for applications such as motor control and digital power applications.
- The peripheral and pin trigger mechanism fully supports touch sensors and other advanced applications.
- Trigger timing occurs in the processor clock domain and requires synchronization to the ADC timing domain.
- Configuration example
- ADnCHxCON1bits.TRG1SRC = 4; // PWM 1 ADC trigger 1
- ADnCHxCON1bits.TRG2SRC = 4; // PWM 1 ADC trigger 2
Trigger Conversion Priority
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Channel priorities influence when each data channel is converted. Recall that the lowest data channel number has the highest priority. For oversampling conversion, it can be made non-interruptible by enabling the Oversampling Burst mode bit (ACCBRST = 1).