Introduction

Contents

In this section, we will cover the primary configurable components of a data channel:

• Primary Configurable Components Overview
• Analog-to-Digital Converter (ADC) Data Channel Support and Priority
• Analog Inputs and Sampling Time
• Sampling Modes, Accumulators, and Interrupts
• Sampling and Conversion Summary
• Conversion Results

Primary Configurable Components Overview

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Each data channel contains the following configurable components:

• Analog positive/negative input selection:
  • Each data channel can select any available analog input for conversion—both positive (external or internal) and, if supported, negative for differential signals. This is set using dedicated register configuration bits. 

• Sample mode and sample time:
  • You can set each data channel to use single or accumulated sampling, and adjust how long the ADC samples the input before converting.

• Data channel conversion triggers:
  • ADC conversions can start from software commands, hardware events (like timers), or other peripherals, allowing precise timing control.

• Data channel result format:
  • The data result format specifies how the converted digital data is presented. Options may include different bit resolutions, signed or unsigned formats, and alignment within the result register.

• Result comparator:
  • Each data channel can use a built-in digital comparator to automatically compare the conversion result against predefined threshold values. If the result meets or exceeds these thresholds, the comparator can trigger specific actions, such as generating an interrupt or flagging an event for further processing.

• Interrupt generation:
  • The ADC can generate interrupts for events like conversion completion, comparator matches, or errors, enabling fast system response.

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Analog-to-Digital Converter (ADC) Data Channel Support and Priority

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This diagram shows that each ADC core (ADC1 to ADC5) supports multiple data channels. Each data channel selects its input using dedicated register configuration bits.

ADC1, ADC2, ADC3, and ADC4 each support up to 8 data channels, and ADC5 supports up to 16 data channels.

Data channels are prioritized by their channel number—the lower the number, the higher the priority.

• This allows you to control which analog signals are processed first, making it easy to set application-specific priorities.
• An example of such is shown in the right column titled Application Benefits. There, you can tailor the natural channel priorities to the importance of a specific analog input.

Channel priority is especially important when multiple channels request conversion at the same time, ensuring the most important signals are handled first.

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Analog Inputs and Sampling Time

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This diagram shows which analog inputs are available for each ADC core.

In this device, ADC1 to ADC4 support up to eight analog inputs each, with ADC5 supporting up to 12 analog inputs.

These inputs include both external pins and internal signals.

Data channels select their analog input using configuration bits that control internal multiplexers and switches:

• ADnCHxCON1.PINSEL[3:0] for positive inputs
• ADnCHxCON1.NINSEL[1:0] for negative inputs

Data channels select their sampling time using the SAMC configuration bits:

• ADnCHxCON1.SAMC[4:0]

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Sampling Modes, Accumulators, and Interrupts

Sampling Modes

Each data channel supports the following sampling modes:

• Single sample conversion:
  • Captures and converts one sample per trigger

• Window sampling (gated accumulation):
  • Continuously accumulates samples while a gate signal is active; stops when the gate signal is de-asserted or a max count limit is reached

• Integration sampling:
  • Accumulates a user-defined number of samples, as set by a counter

• Oversampling:
  • Accumulates a fixed number of samples—choose from 4x, 16x, 64x, or 256x—to improve result resolution and/or reduce noise

• The data channel sampling mode is set via the sampling mode selection bits:
  • ADnCHxCON1.MODE[1:0]

Accumulators

Each data channel contains a primary and a secondary accumulator.

• The primary accumulator supports signal averaging and digital filter implementations.
• The last two data channels for each ADC include a second accumulator, enabling the creation of a second-order filter.

Interrupts

Each data channel has its own interrupt vector for the following events:

• ADC Result Ready (ISR "_ADnCHxInterrupt()"):
  • In single conversion mode, an interrupt is generated after each conversion.
  • In accumulation mode, an interrupt is generated when all samples have been accumulated.

• Result Comparator Event (ISR "_ADnCMPxInterrupt()"):
  • An interrupt is triggered when the conversion result meets/exceeds a defined comparator criterion.

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Sampling and Conversion Summary

In summary, the data channels sample and conversion features enable the application to:

• Assign each selected analog input to its own dedicated data channel for optimized signal processing and control.
• Independently configure the sampling mode and timing for each data channel to optimize performance for every analog input.
• Select the optimal trigger method and timing for capturing conversion data to ensure precise and efficient signal acquisition.

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Conversion Results

In summary, data channel results can be configured to your application's needs:

• Select between single-ended or differential input modes to match your analog input signal requirements.
• Configure the data format as either integer or fractional for seamless integration with your application.
• Access immediate conversion results in ADnCHxRES when operating in single-sample mode.
• Retrieve accumulated data from ADnCHxDATA when using accumulation mode.