Sampling Modes

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The dsPIC33A 12-bit 40 Msps Analog-to-Digital Converter (ADC) provides several data conversion options that support a variety of Digital Signal Processing (DSP) applications.

In this section, we will cover the primary features of the Data Channel Sampling modes:

• Single Sample Mode
• Window Sampling Mode
• Integration Sampling Mode
• 4x Oversampling Mode
• Conversion Result Registers
• Data Formats
• Sampling Modes Benefits (Summary)

The data channel sampling mode is set via the sampling mode selection bits:

• ADnCHxCON1.MODE[1:0]

Single Sample Mode (MODE[1:0] = '00')

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Single Sample conversion mode is a widely used and traditional method suitable for many applications. With the dsPIC33A ADC, you can customize each data channel or individual analog input to match your specific application needs. This mode is selected by setting the MODE[1:0] bits to '00'.

• Application benefits
  • This mode is simple and flexible.
  • It is easy to synchronize a conversion with embedded software.
  • It is ideal for general-purpose and touch sensor applications.

• Operation
  • Each conversion starts with a trigger event. The conversion is triggered by the source selected in the ADnCHxCON1.TRG1SRC[5:0] bits.
  • The result format can be configured as integer or fractional (the ADnCHxCON1.FRAC bit must be set prior to the conversion operation).

• Status and interrupts
  • Upon conversion completion:
    • The result is stored in both ADnCHxDATA and ADnCHxRES registers.
  • Two status flags indicate data readiness:
    • ADnSTAT.CHxRDY: Data is ready in ADnCHxDATA.
    • ADnRSTAT.CHxRRDY: Immediate result is ready in ADnCHxRES.
  • An interrupt flag is set to signal conversion completion.
  • Early interrupt feature support allows for faster system response.

Example Application

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Window Sampling Mode (MODE[1:0] = '01')

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In this mode, the conversion results are accumulated in the ADnDATAx register (primary accumulator) when a signal selected by the TRG1SRC[5:0] bits has an active level.

• Application benefits
  • This mode synchronizes conversions with peripheral activity.
  • It is ideal for applications such as motor control and power conversion.
  • It improves the Signal-to-Noise Ratio (SNR) and smooths the input signal.

• Operation
  • The result format is integer only.
  • Conversions accumulate during a sampling window.
    • Trigger #1 (ADnCHxCON1.TRG1SRC[5:0]) controls the sampling window start.
      • Active trigger level is set by ADnCHxCON1.TRG1POL.
    • Trigger #2 (ADnCHxCON1.TRG2SRC[5:0]) starts each conversion within the sampling window.
      • Results accumulate until the sampling window closes or the maximum count is reached.
      • The number of conversions performed is tracked in the ADnCHxCNT.CNSTAT[15:0] bits.
  • When the window closes or the max count is reached:
    • Accumulated data (integer format) is stored in ADnCHxDATA.
      • The application can calculate the average value using the accumulated sum and the tracked conversion count.
  • Each immediate conversion result is written to ADnCHxRES and must be read before the next conversion, or it will be overwritten.

• Status and interrupts
  • ADnSTAT.CHxRDY indicates accumulated data is ready in ADnCHxDATA.
  • ADnRSTAT.CHxRRDY indicates the immediate conversion result is ready in ADnCHxRES.
  • An interrupt flag is asserted when the result is written to the corresponding result registers.
  • The CHxRDY, CHxRRDY bits and the ADnCHxIF interrupt flag are asserted when the window signal (TRG1SRC[5:0]) is deactivated or when the accumulated conversion count reaches a limit defined by the CNT[15:0] bits in the ADnCHxCNT SFR.

Window Sampling in Motor Control Applications

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Window sampling can be a bonus in motor control applications that require precise current measurement. Current-sense amplifiers measure the voltage across sense resistors in the low-side half-bridge. These signals are valid only when the low-side switches are ON and after a short blanking period.

Window sampling filters signals, estimates derivatives, and corrects sampling time skew. The main objective is to estimate the input signal’s slope during the sampling window.

In this example, three data channels are used in Window Sampling mode.

• Trigger #1 (ADnCHxCON1.TRG1SRC[5:0]) controls the sampling window start.
• Trigger #2 (ADnCHxCON1.TRG2SRC[5:0]) specifies the Pulse Width Modulation P(WM) trigger signal that initiates the sample and conversion operations.

Window Sampling in Power Conversion Applications

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Window sampling offers significant advantages in power conversion, especially for Peak Current mode control with the measurement of average ripple voltage in converters.

In Peak Current mode control, the switch on-time is controlled by monitoring the inductor current and turning the switch off when it reaches a target peak set by an external reference. Average inductor current is measured using PWM timing as the window gate signal.

This approach creates an inner loop for precise current control, while an outer loop adjusts the peak current reference to maintain a stable output voltage.

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Integration Sampling Mode (MODE[1:0] = '10')

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In this mode, the number of conversion results defined by the CNTx[15:0] bits (ADnCNTx[15:0]) is accumulated in the ADnDATAx register (primary accumulator).

The first conversion is initiated by a trigger selected by the TRG1SRC[5:0] bits, and all other conversions are executed by a trigger selected by the TRG2SRC[5:0] bits.

When the number of accumulated conversion results reaches a value in the CNTx[15:0] bits (ADnCNTx[15:0]), the CHxRDY bit in the ADnSTAT register and the ADnCHxIF interrupt flag in the corresponding IFCx register are set.

• Application benefits
  • Conversions are synchronized with peripheral operation.
  • This mode provides an enhanced SNR.
  • It enables effective signal averaging and filtering.
  • It allows measurement of the area under the V(t) analog signal curve.

• Operation
  • The result format is integer-only.
  • This mode accumulates a user-defined number of samples, as specified by the CNT[15:0] bits in the ADnCHxCNT[15:0] SFR.
  • Trigger 1 (TRG1SRC[5:0]) starts the first conversion; Trigger 2 (TRG2SRC[5:0]) starts each subsequent conversion.
  • Sampling stops when the specified count is reached:
    • Accumulated data is stored in ADnCHxDATA.
    • Each immediate conversion result is written to ADnCHxRES and must be read before the next conversion, or it will be overwritten.

• Status and interrupts
  • When the number of accumulated conversion results reaches a value set in the CNT[15:0] bits, in SFR ADnCHxCNT[15:0), the CHxRDY, CHxRRDY and the ADnCHxIF interrupt flags are asserted.

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4x Oversampling Mode (MODE[1:0] = '11')

One method to reduce the amount of noise in an ADC result is to use oversampling. Oversampling is the process of taking multiple measurements of the same signal, then averaging them together. Generally, the number of samples collected is a power of two, which allows the division to be performed by bit-shifting.

This process trades ADC bandwidth for improved data accuracy and resolution.

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• Application benefits
  • This mode enables higher data resolution, up to 13–16 bits from a 12-bit ADC.
  • It reduces device and application noise.
  • It improves SNR for more accurate measurements.

• Operation
  • The result format can be configured as integer or fractional (ADnCHxCON1.FRAC bit must be set prior to conversion operation).
  • The number of samples to accumulate is set by the ACCNUM[1:0] bits (ADnCHxCON1[15:14]) and the accumulated value is written in ADnCHxDATA (primary accumulator). 
  • The first conversion is initiated by a trigger selected by the TRG1SRC[5:0] bits, which also clears the accumulator before the first conversion. 
  • Subsequent conversions are triggered by TRG2SRC[5:0].
    • If ACCBRST (ADnCHxCON2[30]) is asserted, all required samples are taken automatically without further triggers.
    • When ACCBRST is asserted, all other conversions are paused until oversampling completes for the selected data channel. If not asserted, high-priority channels can interrupt the oversampling operation.

• Status and interrupts
  • When the number of the accumulated conversion results reaches a value specified in the ACCNUM[1:0] bits, the CHxRDY bit in the ADnSTAT register and the ADnCHxIF interrupt flag are asserted, and the averaged result may be read from the ADnCHxDATA accumulator.

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Conversion Result Registers

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Each data channel in the dsPIC33A 12-bit 40 Msps ADC contains two result registers:

• ADnCHxDATA, a 32-bit primary accumulator, which is used primarily in multi-sample conversion modes (MODE[1:0] = '01', '10', '11').
  • The ADnCHxDATA register also has its own data ready status bit, ADnSTATbits.CHxRDY.

• ADnCHxRES, a 32-bit immediate conversion result register, which may be used in any conversion mode.
  • The ADnCHxRES register has a dedicated data ready status bit, ADnRSTATbits.CHxRRDY.

Primary Data Accumulator (ADnCHxDATA)

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In each data channel, the primary data accumulator circuit plays a central role in all multi-sampling ADC modes to enable improved measurement accuracy and advanced signal processing.

Let's review how this accumulator is used in the various ADC conversion modes discussed.

• Window mode (MODE[1:0] = ‘01’)
  • The accumulator collects and sums conversion results while a defined sampling window is active. This allows for signal averaging and filtering within a specific time frame, ideal for applications like motor control and power conversion.

• Integration mode (MODE[1:0] = ‘10’)
  • The accumulator gathers a user-defined number of samples, providing effective signal averaging and enabling measurement of the area under the input signal curve. This mode is well-suited for applications requiring precise integration of analog signals.

• Oversampling mode (MODE[1:0] = ‘11’)
  • The accumulator circuitry adds together multiple samples, then computes the average value to increase data resolution beyond the native ADC bit width. Oversampling reduces noise and enhances SNR, delivering higher accuracy for demanding applications.

In each mode, a primary accumulator circuit ensures that multiple conversion results are combined efficiently, supporting advanced filtering, averaging, and resolution enhancement.

Immediate Result Register (ADnCHxRES)

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Starting with the dsPIC33AK512MPS512 family, the ADnCHxRES register always contains the most recent ADC conversion result (immediate result), regardless of sampling mode.

• Each data channel has its own ADnCHxRES register, which is overwritten by the next conversion if not read in time.
• The ADnCHxRES register has a dedicated data ready status bit, ADnRSTATbits.CHxRRDY.

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Data Formats

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The dsPIC33A 12-bit 40 Msps ADC outputs data in integer or fractional formats. Data is either left or right-justified in the result registers, based on the ADnCHxCON1.FRAC bit, with unused bits padded with zeros:

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Sampling Modes Benefits (Summary)

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• Summary of common benefits across all modes
  • All modes provide easy synchronization with embedded code and peripheral state.
  • All modes improve SNR.
  • All modes support signal averaging, filtering, and smoothing.
  • The ADC offers a flexible configuration for a wide range of applications.

• Single Sample mode
  • Single Sample mode provides a simple setup for a broad range of general and touch sensor applications.

• Window Sampling mode
  • Window Sampling mode performs conversions within a variable time window.
  • It is ideal for applications such as motor control and power conversion.
  • It provides enhanced signal smoothing.

• Integration Sampling mode
  • Integration Sampling mode enables accurate measurement of the area under the V(t) analog signal curve

• 4x Oversampling mode
  • 4× Oversampling mode provides higher data resolution, from 13 to 16b.
  • It reduces device and application noise.