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dsPIC33A 12-bit 40MSPS Analog-to-Digital Converter (ADC) Deep Dive

Latency Considerations

Last modified by Microchip on 2026/03/31 11:40
   ADC Latency  Conversion Trigger Examples   

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For the dsPIC33A Analog-to-Digital Converter (ADC), here are the seven key latency components in the sequence of a conversion request to data results.

 Latency Components 
1

Trigger conversion request

Initiates a new ADC conversion.
2

Clock domain synchronization

Ensures the trigger request is properly aligned across different clock domains, resulting in ADC core synchronization timing.
3

Priority resolution

The system determines which data channel to convert first when multiple requests are queued, based on natural channel priority.

4

Data channel identification

The ADC state-machine reads and identifies the specific data channel characteristics associated with a specific conversion request.

5

Sample time period

The minimum sampling time, in the best case, is just 0.5 clock cycles (0.5 TAD).

6

Conversion time

The actual conversion process takes 1.5 clock cycles (1.5 TAD).

7

Data availability

Once conversion is complete, results are written to the data register and are ready for use.

Information

Note: Latency is most noticeable for single conversions. In multi-sample operations, latency is effectively hidden by the continuous processing of queued conversions.