dsPIC33A 12-bit 40MSPS Analog-to-Digital Converter (ADC) Deep Dive
Throughput
Last modified by Microchip on 2026/03/31 11:30
| Conversion Trigger Guidance (continued) | Oversampling: Throughput |
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Running data channel conversions at 40 MHz produces a high volume of data, which can overwhelm the processor and cause data loss if not managed properly.
Key system challenges include:
- Analog-to-Digital Conversion (ADC) throughput: Conversions at 40 MHz must be serviced quickly to prevent data loss.
- Data channel priorities and system bandwidth: The priority scheme ensures simultaneous conversion requests are handled in order, but if high-priority channels dominate, lower-priority channels may experience delays or missed conversions.
To manage high data rates efficiently:
- Leverage system resources such as Direct Memory Access (DMA) and interrupts to offload data handling from the CPU.
- If possible, reduce the conversion rate to a level that allows DMA and interrupts to keep up with data flow, but still meets your system requirements.