Single Conversion Trigger Best Case: Trigger to Data Ready

Click Play ► to listen to the commentary.

This example illustrates single conversion timing when the Analog-to-Digital Converter (ADC) is not busy.

The ADC’s pipelined architecture allows it to handle multiple conversion requests efficiently, accepting new requests even as others are being processed.

Here, we focus on a single trigger event for Channel 0 of ADC1.

Once a channel is selected, the ADC state machine operates in a predictable manner. From the trigger to data availability takes about five clock cycles (with each clock at 12.5 ns, when ADC clock is configured for 80 MHz).

After the sampling period ends (marked as S1 in the timing diagram), the conversion result is available in both the AD1CH0RES and AD1CH0DATA registers in clock cycles.

The conversion time takes ~1.5 ADC clock cycles.

When data is written to the AD1CH0RES and AD1CH0DATA registers, the channel ready flags and the corresponding ADC+Channel interrupt flag are asserted.

The timing diagram visually illustrates this entire process, from trigger to data readiness.

Now, the next step is what do you do with the data.