Single Conversion Trigger Best Case: After Data Ready

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This example illustrates how an application can handle the single conversion Analog-to-Digital Converter (ADC) result once it’s written to the AD1CH0RES and AD1CH0DATA registers.

When data is available, both channel-ready flags and the ADC + channel interrupt flag are asserted, signaling that the result is ready for processing.

At this stage, you have several options for accessing the data, depending on your application’s needs and timing requirements:

• Direct CPU read from the Special Function Register (SFR)
• DMA transfer from the Peripheral to SRAM
• Interrupt Service Routine (ISR) to read the data

In Single Conversion mode, the application can take advantage of early interrupts. When enabled (EIEN bit = ‘1’), the data channel interrupt is generated, and the CH0RRDY bit (in AD1RSTAT register) and CH0RDY bit (in AD1STAT register) are asserted at the start of sampling.

Early interrupts help reduce ISR latency by three ADC clock cycles, allowing for faster response.

The timing diagram illustrates the entire flow—from trigger to data readiness—and highlights the different methods available for processing the conversion result.