Multi-Channel Conversion Trigger

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This example demonstrates a practical scenario for multi-channel conversions.

We build on the core concepts from the two previous examples, applying them to a setup where the SCCP1 peripheral acts as the conversion trigger at a frequency of 40 KHz (or 25 µs period). Importantly, the same trigger is used for all three ADC2 channels—CH0, CH1, and CH2, enabling synchronized conversions across multiple channels.

When the Analog-to-Digital Converter (ADC) pipeline state machine responds to the trigger, all three channels enter the analog pipeline for conversion.

Each channel is processed sequentially, and as each conversion result is written to its data register, the respective channel's ready and interrupt flags are asserted, signaling that the data is available for further processing.

A key point in this example is that the burst of channel data occurs at 40 MHz (meaning three channels are back-to-back-to-back at 40 MHz) and repeats with each trigger period or 40 KHz. This resultant data must be processed quickly—if not, the data will be overwritten or lost.

One effective approach is to set up an interrupt for the last channel conversion, specifically AD2CH2, and use that single ISR to read the conversion results from all three channel conversions.

Using separate interrupts for each channel can become problematic, especially at trigger rates where there is not adequate time between successive triggers/conversions. Each application should carefully evaluate and choose the most efficient method for handling ADC channel conversions.