Single Conversion Trigger Worst Case

Last modified by Microchip on 2026/03/31 11:19

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single conversion worst case

This timing example is much like the previous one, but the Analog-to-Digital Converter (ADC) latency from trigger to data availability is extended by about two ADC clock cycles (25 ns). This extra delay can happen if the ADC is busy or if trigger synchronization is needed, causing the ADC state machine to wait before starting the conversion.

Once the channel request reaches the top of the queue and is serviced, the timing from the sampling period to conversion result is unchanged from the previous example.

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Single Conversion Trigger Worst Case

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