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dsPIC33A 12-bit 40MSPS Analog-to-Digital Converter (ADC) Deep Dive

Input Model - Sampling Time

Last modified by Microchip on 2026/03/31 11:55
   Cross Talk  Signal to Noise Ratio & ENOB   

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Circuit block diagram

To achieve the specified accuracy of the Analog-to-Digital Converter (ADC) module, the holding capacitor (CHOLD) must be given enough time to fully charge to the voltage present on the analog input pin

The total time required for CHOLD to charge is influenced by several factors:

  1. Source Impedance (RSRC): The resistance of the analog signal source
  2. Interconnect Impedance (RIC): The resistance of the Printed Circuit Board (PCB) traces and connections between the source and the ADC input
  3. Sampling Switch Impedance (RSS): The resistance of the internal switch that connects the input to CHOLD

These impedances combine to form the total resistance (Rtotal) in the charging path. In this context, RIC includes RSS.

For accurate sampling, the sampling time must be long enough to allow CHOLD to charge with an error less than half of the least significant bit (0.5 LSB) for a 12-bit ADC.

This requires a minimum sampling time of:

Sampling Time > 9 × Rtotal × CHOLD

This ensures the voltage on CHOLD closely matches the input signal, minimizing conversion errors and maintaining ADC accuracy.