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dsPIC33A 12-bit 40MSPS Analog-to-Digital Converter (ADC) Deep Dive

Direct Memory Access (DMA)

Last modified by Microchip on 2026/03/31 13:19
   System Resources  Data Channel Interrupts   

Peripheral to Memory

DMA Integration

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  • Direct Memory Access (DMA) optimizes system bandwidth by transferring Analog-to-Digital Converter (ADC) data to SRAM for next step processing.
  • The selected DMA channel can perform a peripheral-to-memory transfer without CPU intervention.
    • DMA moves ADC conversion results from the source (peripheral address) to the destination (SRAM address).

When working with the dsPIC33A 12-bit 40 Msps ADC, incorporating DMA can improve system bandwidth by automatically transferring ADC data to SRAM for further processing without burdening the CPU.

The chosen DMA channel handles peripheral-to-memory transfers, moving ADC conversion results directly from the ADC (peripheral address) to SRAM (destination address).

This process frees up CPU resources and enables efficient, high-speed data handling for real-time applications.

DMA Channels

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  • DMA supports up to eight channels (DMA0SEL – DMA7SEL)
    • ADC channel interrupt flag can trigger a DMA transfer:
      • e.g., DMA transfer: Read contents of AD1CH0DATA and write to SRAM buffer

Conversion results are written into the RES data register. The respective channel ready flags are asserted, as well as the channel interrupt flag. The DMA transfer reads the contents of the data register and writes to the SRAM buffer.

  • 110 DMA triggers supported, but we focus on ADC triggers
  • DMA channel triggers: (32 total ADC triggers)
    • ADC1 - CH0 thru CH5
    • ADC2 - CH0 thru CH5
    • ADC3 - CH0 thru CH5
    • ADC4 - CH0 thru CH6
    • ADC5 - CH0 thru CH6

Assign ADC + channel # to a DMA channel

// DMA CH0 trigger for ADC1CH0 

DMA0SELbits.CHSEL = 47;

 

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DMA Peripheral to SRAM Transfers

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DMA peripheral to SRAM transfer example:

Given: CPU clock (FOSC) at 200 MHz, each cycle is 5 ns.

One-shot mode:

Each transfer takes about 10 cycles or 50 ns per transfer event. Here, we're looking at a fixed-to-fixed addressing scheme. That means both the DMA source and DMA destination addresses remain constant for each transfer. In this example, the DMA repeatedly reads from the same channel data register and writes to the same SRAM destination address.

  • 10 cycles (50 ns) for each transfer event
  • Fixed to Fixed Addressing mode, and DMA source and destination addresses remain fixed
  • Set DMAxCNT to a value ≥1, then for each trigger, DMAxCNT is decremented by 1
  • When DMAxCNT = 0, the configured number of transfers is complete and the DMA channel is disabled.

Interrupt mode:

You can enable interrupts for DMA channels to signal transfer completion.

DMA Channel Interrupts

DMA channel 0 ISR name ► _DMA0Interrupt

Refer to the product data sheet for more information on DMA. You'll need to evaluate performance if this meets your requirements.