Analog-to-Digital Converter (ADC) Data Channel Interrupts

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Interrupts allow the system to respond immediately to Analog-to-Digital Converter (ADC) events. Events can be a conversion or a comparison. It removes the need for constant polling and freeing up of CPU resources for other tasks. This leads to more efficient bandwidth usage and improves overall system performance. That means each channel can independently signal the CPU when its conversion is complete. The ADC supports early interrupt generation, a feature that allows the system to react faster to conversion results. This may be useful in time-sensitive applications. Note that the early interrupt feature is only available in the single conversion mode and not in multi-sample or accumulation modes.

• ADC data channel interrupts:
  • ADC1 ► CH0 thru CH7
  • ADC2 ► CH0 thru CH7
  • ADC3 ► CH0 thru CH7
  • ADC4 ► CH0 thru CH7
  • ADC5 ► CH0 thru CH15
• Interrupts for system optimization:
  • Interrupts allow the system to respond immediately to ADC events, removing the need for constant polling and freeing up CPU resources for other tasks. This leads to more efficient bandwidth usage and improved overall system performance.
  • Each data channel can independently signal the CPU when its conversion is complete, enabling precise and timely data handling.
• Early interrupt generation:
  • The ADC supports early interrupt generation, which allows the system to react even faster to conversion results.
  • This feature is especially useful in time-sensitive applications where rapid data processing is critical.

If AD1CH0IF == 1 (interrupt flag is asserted) and AD1CH0IE = 1 (interrupt is enabled), an interrupt is generated for ADC1 Channel 0

The CPU can then execute an interrupt service routine to process the new data immediately.

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Interrupt Latency

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When you look down at the accompanying image, there are two green arrows, one on the left, termed stimulus, and one on the right, termed execute 1st ISR instruction. The time in between these arrows is time latency.

Time latency is derived from four main components:

• t_arb
  • The first component is t_arb, which is the arbitration time used for interrupt priority resolution. When an interrupt occurs, the interrupt controller evaluates it and resolves its priority relative to other pending interrupts.
• Instruction completion time
  • During exception processing, there was an instruction executing. It is complete in one or two cycles.
• IVT Read 
  • The third component is the Interrupt Vector Table (IVT) read time, which represents the vector memory access time.
    • This access takes two cycles from RAM.
    • It takes between four and seven cycles from Flash.
• Program memory access time
  • The fourth component is program memory access time, which is the time required to fetch the first instruction of the Interrupt Service Routine (ISR).

Now you can remap the IVT to RAM and the actual ISR routine into RAM. What you'll see is that the time_{latency minimum} is five cycles or time_{latency max} is six cycles. That's the execution of the first ISR instruction. From Flash, it ranges from nine to 18 cycles. Now interrupts are powerful. They help your application tremendously and remove the burden from the CPU. Ultimately, the use of interrupts will depend on the needs of your application.

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Channel Compare Interrupts

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The interrupts can also be used for compare interrupts. High and low compare thresholds can be configured for each data channel, and interrupts will be generated whether one match or one-to-end matches.

Interrupt for Real-time ADC Data Compare-threshold Alerts

ADC Channel Compare Interrupts:

• ADC1 ► CMP0 thru CMP7
• ADC2 ► CMP0 thru CMP7
• ADC3 ► CMP0 thru CMP7
• ADC4 ► CMP0 thru CMP7
• ADC5 ► CMP0 thru CMP15