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Sleep and Idle Modes

Last modified by Microchip on 2026/03/31 11:14

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Sleep mode

Sleep mode minimizes system noise and power consumption, making it the lowest power state for dsPIC33AK devices.

In Sleep mode, the system oscillator (Fosc) stops, but the Analog-to-Digital Converter (ADC) can continue operating if its clock remains active.

Information

If ADC operation is required during sleep, choose a clock source other than Fosc for the ADC clock.

ADC conversions can be triggered during Sleep, and a conversion interrupt can wake the device, allowing code execution to resume.

In Idle mode, all system clocks remain active, and the ADC continues to operate if enabled.

If the ADC is disabled during Sleep or Idle, re-enabling it requires approximately 5,000 calibration cycles. For example, with an ADC clock of 80 MHz (TAD = 12.5 ns), calibration takes approximately 62.5 µs.

Information

Note: To avoid this long start-up time, the recommended method to reduce power is to put the module in Standby mode, which only requires 200 clocks to re-enter operation.