dsPIC33A Hardware Configuration

Overview

Software needs hardware!

Before you can develop firmware for a dsPIC33A device in MPLAB^® X IDE, you need to develop a functional hardware schematic and understand some basic hardware configuration defaults, so your firmware can successfully execute on the target.

This page reviews the required dsPIC33A basic pin connections and where to locate this information in the device data sheet. We’ll also review the clock system default configuration, other hardware defaults, and how to set configuration bits in C code to change these default hardware settings.

Required Pin Connections

VDD/VSS and AVDD/AVSS

All VDD/VSS pins must be properly biased with the required supply voltages. This includes the AVDD/AVSS pins, even if no analog functionality is used in your application.

Decoupling capacitors are recommended for use on every pair of VDD/VSS and AVDD/AVSS pins. Refer to the data sheet for details on the recommended values.

MCLR

The MCLR pin is used to perform a device reset and is also used in programming and debug operations.

A pull-up connection to the reset or Master Clear (MCLR) pin is required to keep the device in a normal (non-reset) state. This can be as simple as a 4.7k to 10k pull-up resistor from the MCLR pin to VDD, but the recommended option is to use an RC circuit (10k and 0.1 uf) from VDD to ground with a small value series resistor (100 to 470 ohm) from the center of the RC connection to the MCLR pin. This will give a slower rise time on the MCLR pin and allow more time for VDD to stabilize.

The series resistor limits current flow into the MCLR in the event of an internal MCLR pin breakdown.

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PGC/PGD

Programming and debugging connections, also known as the In-Circuit Serial Programming (ICSP) connections, are only required for firmware development and not the operation of the device.

There are five connections required to connect a programmer and debugger tool (such as a PICkit™ 5) to the device. These five connections include:

• The VDD and VSS pins
• The MCLR pin
• Plus the ICSP pins: PGC (Clock) and PGD (Data)

Optionally, you can also connect the dsPIC33A serial Universal Asynchronous Receiver Transmitter (UART) TX and RX pins to the PICkit 5 pin header since this debugger enumerates a USB CDC connection, allowing serial data to be exchanged between the dsPIC^® device and a Terminal application running on the PC.

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Clock System Configuration

The dsPIC33A clock system provides clock signals to the CPU and peripherals. The module is based on a number of clock generators (CLKGENs) and PLL generators (PLLGENs). The CLKGENs are preassigned to the CPU and peripherals. Each clock generator selects a clock source from the available oscillators or PLLs and passes it to a selectable divider circuit. CLKGEN1 provides the clock signals for the CPU and peripherals.

Default Configuration

On reset, CLKGEN1 is enabled with the 8 MHz FRC oscillator source. This provides an 8 MHz clock for the CPU, and  8, 4, and 2 MHz clocks for the fast, standard, and slow peripheral clocks, respectively, after reset.

For more details, visit the dsPIC33A Clock System page.

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Configuration Bits

It is unlikely that a new C program will run properly on the device, even though the program is valid.

All Microchip microcontrollers must be configured to ensure correct hardware operation. Some device configuration settings affect the fundamental operation of the device, such as those controlling the instruction clock. The configurable hardware options are in the data sheet chapter titled Configuration Bits.

To configure the device, the source code must include a series of #pragma config configuration options as shown here:

See the following instructions for locating the #pragma config key/value pairs for all configuration bit settings for your device.

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Locating Available Configuration Key/Value Settings for Your MCU

This involves locating a specific HTML documentation file on your PC.