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Architecture

Last modified by Microchip on 2026/04/01 10:27

Overview

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The interrupt controller acts as the system’s traffic manager for all peripheral interrupts and exceptions. It processes these events before they ever reach the CPU. Using centralized special function registers, the controller enables, prioritizes, and manages both interrupts and traps, ensuring that critical events are handled efficiently and in the correct order.

  • The interrupt controller collects all peripheral interrupt requests and assigns priorities.
  • It sends the highest-priority unmasked interrupt to the CPU using a vector number from the Interrupt Vector Table.
  • It supports programmable priorities, six processor traps, and other generic traps.

How It Works

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Interrupt Services

  1. Interrupt Sources
    • Sources consist of peripherals, external pins, and system traps. Except for traps, each interrupt has its own enable and priority settings.

      Note: Traps are non-maskable, so they are always enabled.

  2. Interrupt Controller
    • The interrupt controller handles interrupts and exceptions before they reach the CPU. It uses special function registers to enable, prioritize, and control these events. The IFSx registers check for interrupt requests every clock cycle. If a flag is set, it means an interrupt is waiting.
  3. CPU
    • The CPU reviews the priorities of all pending interrupts. If any interrupt has a higher priority than the current processor level, the CPU will respond to it. Important interrupt details—like the vector number and priority level—are stored in the INTTREG register. The IACK signal locks these details to keep them stable during the interrupt process.
  4. Interrupt Service Routine (ISR)
    • Before handling the interrupt, the CPU saves the current program counter and the status register’s low byte, which includes the current priority level. This ensures a smooth and reliable transition into the ISR.

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Interrupt Example

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Interrupt Service Routine

When the CPU receives an interrupt request, its details are saved in INTTREG.

Steps for executing the ISR:

  1. INTTREG: Holds CPU interrupt priority level and vector # until the next interrupt comes to the CPU
  2. Pre-ISR:
    • Push status <SR[23:0]> to Top of Stack “TOS”
    • Push PC <0x00,PC[23:1],0b0> to TOS
  3. ISR executes and completes
  4. Post-ISR:
    • Restore PC <0x00,PC[23:1],0b0> from TOS
    • Restore CPU Status <SR[23:0]> from TOS
    • Continue with main program flow