Monitor and Control Operations

Introduction

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In this section, we discuss the key monitor and control registers of the interrupt controller, its advanced features, and support for interrupt nesting that enables efficient handling of multiple interrupts. We also describe the hardware context management performed during interrupts to ensure smooth transitions and reliable operation, and explain how the system wakes from Sleep and Idle modes for fast recovery from low‑power states.

Monitor and Control Registers

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• For monitoring purposes
  • Use INTCON3 to monitor bus error traps and INTCON5 for software and generic traps.

• For monitoring and control purposes
  • INTCON1 shows CPU error traps and lets you set global interrupt and nesting features.
  • INTCON4 handles the accumulator and math traps.
  • IFS0–IFS11 registers display and set peripheral interrupt flags.
  • INTTREG displays Interrupt Request (IRQ) CPU status, CPU Interrupt Priority Level (IPL), and vector numbers.

• For control purposes
  • INTCON2 sets external interrupt edge polarity.
  • IEC0–IEC11 registers enable or disable interrupts.
  • IPC0–IPC46 registers set interrupt priority levels.
  • IVTBASE sets the interrupt vector base address.
  • IVTCREG sets the base address for collapsed interrupt vectors.

Features

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Peripheral Interrupts

You can enable or disable each interrupt by setting or clearing its bit in the IEC0–IEC11 registers. For example, IEC1bits.INT0IE = 1 enables INT0, while IEC1bits.INT0IE = 0 disables it (the default after reset). This allows precise control over which interrupts are active.

Global Interrupts

You can also enable or disable all interrupts at once using the global interrupt bit (INTCON1bits.GIE). Setting GIE = 1 enables all interrupts (default after reset); setting GIE = 0 disables them, but traps stay active. Global control is useful for protecting critical code or handling system-wide events.

Raising CPU Interrupt Priority Level

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Setting the CPU’s IPL to 7 (SRbits.IPL = 7) blocks all interrupts, as we see noted in the table. A key point to note is that traps remain enabled. Setting SRbits.IPL = 0 allows all interrupts (default after reset). This method gives finer control than just using the global interrupt enable bit.

Interrupt Nesting

The NSTDIS bit controls interrupt nesting. INTCON1bits.NSTDIS = 1 disables nesting, blocking other interrupts during an Interrupt Service Routine (ISR). INTCON1bits.NSTDIS = 0 enables nesting, letting higher-priority interrupts preempt the current ISR (default after reset). These settings help you control how the system handles multiple interrupts.

Example

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This example demonstrates how interrupt nesting works.

While the main code is executing and interrupt nesting is enabled, ISR_1() interrupts the main program flow. As ISR_1() is executing and before it completes, a higher-priority interrupt occurs, causing ISR_2() to interrupt ISR_1(). The context of ISR_1() is then placed on the stack.

The dsPIC33A device automatically switches context to ISR_2(), and when ISR_2() finishes, a RETFIE instruction restores the ISR_1() context and returns execution to ISR_1().

After ISR_1() completes, another RETFIE instruction returns the program back to the main code. Throughout this entire process, the processor context and status are maintained.

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Interrupt Controller Hardware Context

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The CPU has a base context and seven hardware contexts (Context 1–7), each linked to a specific interrupt priority level. When an exception occurs, the CPU saves the current status and program counter and then switches to the hardware context associated with the interrupt priority level of the ISR.

After the ISR, the CPU restores the previous context to continue normal operation. Each context includes registers W0–W7, Accumulators A and B, RCOUNT, and Digital Signal Processing (DSP)-related Core Control Register (CORCON) control bits such as US, SATA, SATB, SATDW, ACCSAT, RND, and IF.

If interrupt nesting is disabled, all ISRs use Context 7 regardless of the interrupt’s priority level, and IPL[2:0] becomes read-only.

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Trap Nesting

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The IPL[3] bit indicates when a trap is active. This bit can be cleared by software but only set by hardware.

Traps have higher priority than user interrupts, so critical errors are handled first. The processor sets the IPL3 bit when a trap occurs. Clearing IPL3 in software lets your application redirect execution or continue processing after a trap.

This mechanism allows your application to jump to a different instruction, not just the one immediately after the instruction that caused the trap, providing greater control over error recovery and system flow.

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PCTRAP

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The PCTRAP Trap Origination Address register captures the program counter address at which a CPU-generated trap error occurred, but only if the current Interrupt Priority Level (IPL) is less than eight. If the priority is eight or higher, PCTRAP does not record the address.

Once set, PCTRAP is locked to keep the original trap location for debugging. This feature is especially useful for debugging, as it helps you pinpoint exactly where a system trap originated.

To capture a new trap address, clear PCTRAP by writing 0x000000 to it.

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Disable Interrupts Instruction

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The DISICTL instruction lets you temporarily disable interrupts during critical code sections. With DISICTL, you can select which interrupt priority levels to block for precise control.

The current IPL threshold value is shown in the read-only DISIIPL[2:0] register. You can set the threshold using a 3-bit value or a register source. The new threshold is immediately updated in the DISIIPL register.

This feature is essential for protecting critical code and maintaining system stability and deterministic behavior

Disable Interrupts Example

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The previous DISI instruction has been replaced by DISICTL(W) for better management and control. DISICTL(W) disables interrupts at or below the set IPL threshold, which you choose with a literal value or a Wns register. See the basic example shown.

You can always check the current threshold in the DISIIPL[2:0] register.

For nested use, DISICTL(W) can also save the previous IPL, making it easier to restore interrupt settings after critical code.

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Wake-up From Sleep and Idle

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When the interrupt controller gets an interrupt or trap request, it sends a wake-up signal to the CPU if it’s in Sleep or Idle mode.

The CPU checks the interrupt’s priority:

• If the IPL is higher than the CPU’s current priority, the CPU runs the ISR. Traps always remain enabled.
• If the IPL is equal to or lower, the CPU continues with the next instruction after PWRSAV.

Interrupts with priority level zero are fully disabled—they can’t trigger or wake up the CPU.