dsPIC33A Interrupt Controller

External Interrupts

Last modified by Microchip on 2026/04/07 10:31

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External Interrupts

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dsPIC33AAK512MPS510 External Interrupt Block Diagram

There are five external interrupts available: INT0 through INT4. Each interrupt can be configured to detect either a rising (positive) or falling (negative) edge, providing flexibility for different signal types. Edge detection settings for these interrupts are controlled by INT0EP through INT4EP bits in the INTCON2 register.

You can set the priority level for each interrupt using the INTnIP[2:0] bits (where n = 0 through 4).

To enable these interrupts, use the IEC1 register, and monitor their status with the IFS1 register.

INT0, INT1, and INT2 can also be used to trigger DMA transfers, allowing for efficient data movement without CPU intervention.

Additionally, input pin remapping is supported, so you can assign these interrupt functions to different physical pins as needed for your design.

External Interrupt Inputs

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dsPIC33AAK512MPS510 INT0 - INT2 Interrupt Block Diagram

INT0, INT1, and INT2 can be used as input signals for Capture/Compare/PWM (CCP) synchronization and triggering. In Sync mode, the CCP timer runs continuously and resets to zero whenever an INT0 through INT2 input is asserted. In Trigger mode, the CCP timer remains at zero until one of the INT0 through INT2 inputs is asserted; only then does the timer begin counting. These modes allow precise control over timer operation, enabling accurate event timing and synchronization in your application.