Peripheral Interrupts

Introduction

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In this next section, we’ll focus on three important topics:

• Peripheral interrupts
• External interrupts
• System traps

We’ll look at how peripheral interrupts are generated and managed within the microcontroller. Then, we’ll cover external interrupts, which respond to signals from outside the device. Finally, we’ll discuss system traps, which handle critical errors and special conditions to keep the system running safely.

Peripheral Interrupts

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The system enables up to 272 different peripheral interrupt sources, providing extensive flexibility for complex and diverse applications.

All peripheral interrupts are maskable, meaning you can enable or disable them as needed for your application.

Many peripherals, such as Analog-to-Digital Converters (ADCs) and Pulse-Width Modulation (PWM) modules, use multiple interrupt vectors to support their wide range of features.

For example, ADC1 through ADC5 can generate up to 96 interrupt sources, while the PWM module offers 18.

Unlike traps, you only need to add interrupt handlers for the specific peripheral features your application is actually using.

Calculating Vector Address

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The vector address is calculated using both the interrupt request number and the value of the base register, IVTBASE.

IVTBASE provides an offset that determines the starting address of the Interrupt Vector Table (IVT). This allows interrupt vector addresses to be flexibly mapped to any location within user Flash or user RAM, giving developers control over where interrupt vectors reside in memory.

To calculate the address in the vector table where a particular peripheral interrupt vector resides, refer to Example 1 and Example 2 as shown.

Example 1: Interrupt #33 -> External INTO Interrupt

Resultant address = (0x80A000(hex) + 33x4 (dec) (convert to hex) + 24(hex) = 0x80A0A8(hex)

Example 2: Interrupt #33 -> Default After a Device Reset

Resultant address = (0x800000(hex) + (33x4(dec) (convert to hex)) + 24(hex) = 0x8000A8(hex)

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External Interrupts

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There are five external interrupts available: INT0 through INT4.

Each interrupt can be configured to detect either a rising (positive) or falling (negative) edge, providing flexibility for different signal types.

Edge detection settings for these interrupts are controlled by INT0EP through INT4EP bits in the INTCON2 register.

You can set the priority level for each interrupt using the INTnIP[2:0] bits. (where n = 0 through 4).

To enable these interrupts, use the IEC1 register, and monitor their status with the IFS1 register.

INT0, INT1, and INT2 can also be used to trigger Direct Memory Access (DMA) transfers, allowing for efficient data movement without CPU intervention.

Additionally, input pin remapping is supported, so you can assign these interrupt functions to different physical pins as needed for your design.

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External Interrupt Inputs

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INT0, INT1, and INT2 can be used as input signals for Capture/Compare/PWM (CCP) synchronization and triggering.

In Sync mode, the CCP timer runs continuously and resets to zero whenever an INT0 through INT2 input is asserted.

In Trigger mode, the CCP timer remains at zero until one of the INT0 through INT2 inputs is asserted; only then does the timer begin counting.

These modes allow precise control over timer operation, enabling accurate event timing and synchronization in your application.