System Traps

Introduction

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There are 18 types of traps in total. These include:

• seven processor error traps,
• one address error,
• four bus errors,
• one illegal instruction error,
• one stack error,
• six math errors,
• four general errors, and
• one software-generated trap.

Out of the 18 traps, 15 are non-maskable, meaning they cannot be disabled.

The three maskable traps are Accumulator A and B overflow (2), and catastrophic overflow for Accumulator A/B (1).

Types

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Bus error traps monitor each main bus and are flagged in INTCON3. Illegal instruction traps catch invalid or misaligned instructions. Address error traps detect misaligned data access. Stack error traps trigger if the stack pointer goes out of range. Math error traps handle divide-by-zero and overflows, managed in INTCON4. Software traps, Direct Memory Access (DMA) errors, and watchdog events all generate a Generic Trap, and their status is recorded in INTCON5.

Bus Error Traps

There are four bus error traps, each associated with the instruction bus (I‑bus), X‑bus, Y‑bus, and the DMA bus.
A bus error trap is generated by a bus matrix initiator when either the Bus Matrix (BMX) or the target device reports an error during a transaction.

Each bit within the INTCON3 register is assigned to a specific bus error condition.

Illegal Instruction Error Trap

The illegal instruction error trap is associated with an attempt to execute an illegal opcode. This trap is triggered by an unimplemented co-processor instruction or Program Flow Change (PFC) to odd addresses of 32-bit instructions

Address Error Trap

This trap will be taken as a result of misaligned data word access.

Stack Error Trap

Math Error Traps

Math error traps are associated with divide‑by‑zero conditions, accumulator overflows (both catastrophic and non‑catastrophic), and accumulator shift operations that exceed the allowed range.

The associated status and enable bits are present in the INTCON4 register.

Generic Traps

A generic trap is taken when any of the status bits in the INTCON5 register are set. Bits in INTCON5 are associated with software traps, DMA address errors, and watchdog or deadman timer events.

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Traps are special interrupts that cannot be masked or disabled, ensuring they are always recognized by the system. They can be nested and have fixed priority levels.

Traps play a crucial role in error handling, as they help detect and correct faults during both debugging and normal application operation.

For most traps, the instruction that caused the trap will finish executing before the exception is processed. This means your application may need to take corrective action for any effects caused by that instruction.