dsPIC33A Interrupt Controller
Vector Table Characteristics
| System Traps | Performance |
Introduction
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The Interrupt Vector Table (IVT) is stored in program memory or RAM and serves as the central directory for all interrupt and trap handling. The IVT includes entries for all interrupt vectors, as well as six dedicated processor trap vectors. Each interrupt vector entry contains a 24-bit address, which points to the first instruction of its corresponding Interrupt Service Routine (ISR). When an interrupt occurs, the processor core reads the IVT and loads the 24-bit address from the appropriate vector directly into the Program Counter, ensuring a fast and accurate jump to the ISR.
After a device reset, the IVT base address defaults to 0x800000. The processor starts code execution at the address specified by the reset vector located at this base address. Developers can also set a different IVT base address using the IVTBASE register. This feature allows you to erase or reprogram user code without disturbing the vector table.
How It Works
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| Priority Order | Interrupt "Vector" Source | Vector Number | Maskable |
|---|---|---|---|
| Highest | Reset Vector | No | |
| Traps | 2 - 8 | ~No | |
| Common Collapsed Vector | 9 | Yes | |
| FPU | 10 | Yes | |
| XRAM ECC SE | 11 | Yes | |
| YRAM ECC SE | 12 | Yes | |
| PBU Parity Error | 13 | Yes | |
| NVM ECC SE | 14 | Yes | |
| NVM Program/Erase Com. | 15 | Yes | |
| NVM CRC Complete | 16 | Yes | |
| Combined Clock Fail | 18 | Yes | |
| Peripheral/Feat. 10 - 271 | 19 - 363 | Yes | |
| Lowest | APWM Event D (272) | 364 | Yes |
The reset vector has a fixed address and the highest priority in the system, ensuring the processor always starts execution from a known location after a reset. Interrupt vector sources are assigned fixed priorities, arranged from highest to lowest, so critical events are always handled first.
The IVT offers advanced features. It can be remapped to a new location in memory, Remappable Interrupt Vector Table (RIVT), or collapsed to save space, Collapsed Interrupt Vector Table (CIVT), giving you flexibility in system design. There is also a vector fail address feature, which provides a safe fallback if the processor cannot fetch a valid vector from the table, helping to maintain system stability and reliability.
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Most traps—about 83%—are non-maskable, meaning they cannot be disabled and will always be recognized by the system. However, three out of the six math error traps are maskable. These include Accumulator A/B Catastrophic Overflow, Accumulator A Overflow, and Accumulator B Overflow, giving you some flexibility in how these specific errors are handled.
In contrast, all standard interrupts are maskable, so you can enable or disable them as needed.
The best practice is to provide handlers for all traps, even if you don’t plan to use them. This ensures your system responds predictably and safely to unexpected events.
If a trap isn’t needed, we recommend using a software reset as the handler. This approach helps maintain system stability and prevents unpredictable behavior.
Interrupt Vector Tables
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There are three ways to organize IVTs:
- Full IVT Mode: Each interrupt or exception has its own vector for dedicated handling.
- Collapsed IVT Mode: All peripheral interrupts use one vector; software must identify the source.
- Remappable IVT Mode: Each interrupt has a unique vector, and the table can be moved anywhere in Flash or RAM.
Each vector entry stores the address of its Interrupt Service Routine (ISR).
When an interrupt happens, the CPU reads the IVT and loads the ISR address into the program counter for quick response.
Full Interrupt Vector Table
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The reset vector always starts at the fixed address, 0x800000, in user memory. By default, the IVT is in full mode, meaning each peripheral has its own dedicated interrupt vector. The table is not collapsed, as indicated by IVTC = 0. Every peripheral is assigned a unique interrupt vector and has its own control features, allowing precise and independent event handling. The IVT is initially located in program memory at address 0x800000. If needed, you can relocate the IVT to any valid address in Flash or RAM by updating the IVTBASE register, giving you flexibility in memory management and system design.
Collapsed Interrupt Vector Table
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The reset vector is always at address 0x800000 for a consistent startup. In collapsed IVT mode (IVTC = 1), all peripheral interrupts use one vector. Priority, enable, and status for the collapsed vector are managed in IPC0, IEC0, and IFS0 registers. Collapsing the table puts all handlers in one place, making management easier at the trade-off of response time. A collapsed table approach may also provide benefits in secure based application. The CIVT register can be write-locked for added safety and reliability.
Remappable Interrupt Vector Table
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The reset vector is always at address 0x800000. By default, the IVT also starts at 0x800000. With RIVT, you can move the IVT to any address using the IVTBASE register for flexible memory use. IVTBASE can be write-locked to prevent unwanted changes. Both full and collapsed IVTs can be relocated, depending on application needs. This lets you update or erase user code without affecting the IVT, making firmware updates safer. RIVT also allows runtime changes to the vector table for secure and dynamic interrupt handling.
Remapping IVT in Immutable Root of Trust (IRT) Mode
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When running in boot or secure memory, the processor can set up a temporary IVT in the secure region by updating IVTBASE. If a trap or interrupt happens, secure boot fetches the vector from this protected IVT. Secure boot software can also collapse the IVT, combining all peripheral interrupts into one vector. After finishing, the secure software can restore the default IVT.
Vector Fail Address
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The Vector Fail Address (VFA) is designed to handle situations where the processor cannot successfully fetch a vector from the interrupt table. For example, if a bus error occurs while reading a vector location, the system might retrieve an incorrect address, potentially causing the program to jump to an invalid location.
Scenario to Consider
A bus error while reading a vector location can be serious, since it may return an incorrect vector value. This could result in PFC being sent to an invalid address. In these cases, VFA holds the alternate routine address for the required action.
The default value of VFA[23:0] must be the contents of the reset vector @0x800000, for a safe program restart.
In these cases, the VFA provides an alternate routine address, ensuring the system can take appropriate action and maintain stability. To guarantee a safe restart, the default value of VFA[23:0] should match the contents of the reset vector at address 0x800000.
Reset Vector
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The reset vector is where the CPU fetches its first instruction after a reset. It is always fixed at address 0x800000 and is not part of the IVT. Changing or moving the IVT does not affect the reset vector’s address or function. The reset vector directly holds the start address, not a jump instruction. On reset, the processor clears its registers, sets the program counter to 0x800000, and begins execution from there. This ensures the system always starts at the correct routine after a reset.