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SAM9X60 Series

Last modified by Microchip on 2025/08/04 15:19

SAMA5D2
The SAM9X60 is a high-performance, ultra-low power Arm926EJ-S™ CPU-based embedded microprocessor (MPU) running up to 600 MHz, with support for multiple memories such as Synchronous Dynamic Random-Access Memory (SDRAM), LP-SDRAM, Low-Power Double Data Rate (LPDDR), Double Data Rate type two (DDR2), Quad SPI Interface (QSPI), and e.MMC Flash. The device integrates powerful peripherals for connectivity and user interface applications, and offers security functions (tamper detection, secure boot program, secure key storage, etc.), True Random Number Generator (TRNG), as well as high-performance crypto accelerators for Advanced Encryption Standard (AES) and Secure Hash Algorithm (SHA). The SAM9X60 series is delivered with a comprehensive development suite that includes a mainline Linux® distribution and Microchip's MPLAB® X IDE and MPLAB Harmony v3 software framework. 

Key Features

  • Powered by an Arm926EJ-S™ Arm® Thumb® processor architecture running up to 600 MHz
  • 32 KB data cache, 32 KB instruction cache, Memory Management Unit (MMU)
  • Memories
    • One 160 KB internal ROM
      • 64 KB internal ROM embedding a secure bootloader program supporting boot on NAND Flash, SD™ card, Serial Peripheral Interface (SPI) or QSPI Flash
      • 96 KB ROM for NAND Flash BCH ECC table
    • One 64 KB internal SRAM (SRAM0), single-cycle access at system speed
    • High-bandwidth multi-port DDR2/LPDDR controller
    • 32/16-bit External Bus Interface (EBI) supporting 8/4-bank DDR2/LPDDR, 4/2-bank SDR/ LPSDR, static memories, with scrambling
    • NAND Flash controller, with up to 24-bit programmable multi-bit error correcting code
    • One 11 KB One-Time Programmable (OTP) memory for secure key storage with emulation mode 
  • System running up to 200 MHz
    • Power-on Reset (POR) cells, Reset Controller (RSTC), Shutdown Controller (SHDWC), Periodic Interval Timer (PIT), Watchdog Timer (WDT), and Real Time Clock
    • Two internal trimmed RC oscillators with typical values: 32 kHz (slow) and 12 MHz (fast)
    • Two crystal oscillators: 32.768 kHz (slow) and 12 to 48 MHz (fast)
    • One Phase-Locked Loop (PLL) for the system and one PLL optimized for USB high-speed operation (480 MHz)
    • One dual-port 16-channel Direct Memory Access (DMA) controller
    • Advanced Interrupt Controller and Debug Unit
    • JTAG port with disable bit in OTP memory
    • Two programmable clock output signals
  • Low-power modes
    • Backup mode with Real-Time Clock (RTC), eight 32-bit general purpose backup registers, and Shutdown Controller
    • Clock Generator and Power Management Controller (PMC)
    • Software-programmable ultra-low power modes:
      • Very Slow Clock operating mode (ULP0),
      • No-Clock operating Mode (ULP1) with fast wake-up capabilities
  • Peripherals
    • LCD controller with overlay, alpha-blending, rotation, scaling, and color conversion
      • Up to 1024 x 768 resolution
    • 2D graphics controller
    • ITU-R BT. 601/656 up to 12-bit Image Sensor Interface (ISI)
    • One USB Device High Speed, three USB Host High Speed 
    • Two 10/100 Mbps Ethernet MAC Controller
    • Two 4-bit Secure Digital MultiMedia Card Controller (SDMMC)
    • Two CAN Controllers
    • One Quad I/O SPI Controller
    • Two three-channel 32-bit timers/counters
    • One high-resolution (64-bit) PIT
    • One Synchronous Serial Controller (SSC)
    • One Inter-IC Sound Multi-Channel Controller (I2SMCC) with Time Division Multiplexed (TDM) support
    • One Audio Class D Controller with single-ended or bridge-tied load connection to power stage
    • One four-channel 16-bit PWM Controller
    • Thirteen FLEXCOMs (USART, SPI, and TWI)
    • One 12-channel 12-bit Analog-to-Digital Converter (ADC)
  • Hardware cryptography
    • SHA (SHA1, SHA224, SHA256, SHA384, SHA512) and Keyed-Hash Message Authentication Code (HMAC) compliant with FIPS PUB 180-2
    • AES: 256-, 192-, 128-bit key algorithms, compliant with FIPS PUB 197
    • TDES: two-key or three-key algorithms, compliant with FIPS PUB 46-3
    • TRNG
  • I/O ports
    • Four 32-bit Parallel Input/Output Controllers
    • Up to 112 programmable I/O lines 
  • Qualification
    • AEC-Q100 Grade 2 ([-40°C to +105°C] ambient temperature). Applies to -V/DWBVAO devices only.
  • Operating conditions
    • Ambient temperature range (TA): -40°C to +105°C
    • Junction temperature range (TJ ): -40°C to +125°C
  • Packages:
    • 11 mm x 11 mm, 0.65 mm pitch, 228-ball  Thin Profile Fine Pitch Ball Grid Array (TFBGA) optimized for standard class Printed Circuit Board (PCB) layout (down to four layers)
    • 9 mm x 9 mm, 0.5 mm pitch, 256-ball BGA for space-constrained applications

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