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SAM9X7 Series

Last modified by Microchip on 2025/08/11 12:04

SAMA5D2
The SAM9X7 series microprocessors are high-performance and cost-optimized Arm926EJ-S™ CPU-based embedded microprocessors (MPUs), running up to 800 MHz. The devices integrate powerful peripherals for connectivity and user interface applications, including MIPI® DSI®, Low-Voltage Differential Signaling (LVDS) controller, RGB and 2D graphics, MIPI CSI-2®, Gigabit Ethernet with Time-Sensitive Networking (TSN) and CAN-FD. Advanced security functions are offered, such as tamper detection, secure boot, secure key storage, True Random Number Generator (TRNG), Physically Unclonable Function (PUF) as well as high-performance crypto accelerators for Advanced Encryption Standard (AES) and Secure Hash Algorithm (SHA). The SAM9X60 series is delivered with a comprehensive development suite that includes a mainline Linux® distribution and Microchip's MPLAB® X IDE and MPLAB Harmony v3 software framework. 

Key Features

  • Powered by an Arm926EJ-S Arm® Thumb® processor architecture running up to 800 MHz
  • 32 KB data cache, 32 KB instruction cache, Memory Management Unit (MMU)
  • Memories
    •  One 176 KB internal ROM
      • 80 KB internal ROM embedding a secure bootloader program supporting boot on NAND Flash, SD card, Serial Peripheral Interface (SPI) or Quad Serial Peripheral Interface (QSPI) Flash
      • 96 KB ROM for NAND Flash Bose–Chaudhuri–Hocquenghem (BCH) Error-Checking and Correction (ECC) table
    • One 64 KB internal SRAM (SRAM0)
    • DDR3(L)/DDR2 controller running at up to 266 MHz
    • External Bus Interface (EBI) supporting:
      • 16-bit 8/4-bank DDR3(L)/DDR2
      • 16-bit static memories
      • 8-bit NAND Flash with up to 24-bit programmable multi-bit error correcting code
    • One 10 KB One-Time-Programmable (OTP) memory for secure key storage with Emulation mode (OTP bits are emulated by a 4 KB SRAM (SRAM1))
  • System Running up to 266 MHz
    • Power-on Reset (POR) cells, Reset Controller (RSTC), Shutdown Controller (SHDWC), Periodic Interval Timer (PIT), Watchdog Timer (WDT), and Real-Time Clock (RTC) running
    • Two internal trimmed RC oscillators with typical values: 32 kHz (slow) and 12 MHz (fast)
    • Two crystal oscillators: 32.768 kHz (slow) and 20 to 50 MHz (fast)
    • One Phase-Locked Loop (PLL) for the system and one PLL optimized for USB high-speed operation, audio operations, LVDS I/F, MIPI D-PHY℠
    • One dual-port 16-channel Direct Memory Access (DMA) controller
    • Advanced interrupt controller and debug unit
    • JTAG port with disable bit in OTP memory
    • Two programmable clock output signals 
  • Low-Power Modes
    • Backup mode with RTC, eight 32-bit general-purpose backup registers, and shutdown controller
    • Clock generator and power management controller
    • Software programmable power optimization capabilities
    • Software-programmable ultra-low power modes:
      • Very slow clock operating mode (ULP0)
      • No-clock operating mode (ULP1) with fast wake-up capabilities
  • Peripherals
    •  LCD controller with overlay, alpha-blending, rotation, scaling and color conversion; display size up to 1024x768 (XGA) and RGB, LVDS, MIPI DSI interfaces
    • 2D graphics controller
    • Image sensor controller with ITU-R BT
    • One high-speed USB device, three high-speed USB hosts
    • One 10/100/1000 Mbps Ethernet MAC controller
    • Two CAN-FD controllers with timestamping
    • One quad/octal SPI controller
    • Two 3-channel 32-bit timers/counters
    • Two high-resolution (64-bit) periodic interval timers
    • One synchronous serial controller
    • One inter-IC sound multi-channel controller with Time Division Multiplexing (TDM) support
    • One audio class D controller with single-ended or bridge-tied load connection to power stage
    • One 4-channel 16-bit Pulse-Width Modulator (PWM) controller
    • Thirteen FLEXCOMs (USART, SPI and TWI/I2C)
    • One 8-channel, 12-bit, analog-to-digital converter 
  • Hardware Cryptography
    • SHA (SHA-1, SHA-224, SHA-256, SHA-384, SHA-512) and Keyed-Hash Message Authentication Code (HMAC) compliant with FIPS PUB 180
    • AES: 256, 192, 128-bit key algorithms compliant with FIPS PUB 197
    • AES/SHA tight coupling for IPsec hardware acceleration
    • TDES: 2-key or 3-key algorithms compliant with FIPS PUB 46
    • True random number generator
    • Key bus providing private key transfers between AES, TDES, TRNG, OTPC
    • Physical Unclonable Function (PUF) including NIST SP 800-90B (DRNG) and embedding four Kbytes of SRAM (PUFSRAM)
  • I/O Ports
    • Four parallel input/output controllers
    • Up to 106 programmable I/O lines multiplexed with up to four peripheral I/Os
    • Input change interrupt capability on each I/O line, optional Schmitt trigger input
    • Individually programmable open-drain, pull-up and pull-down resistors, synchronous output
    • General-purpose analog and digital inputs tolerant to positive and negative current injection
  • Designed for low ElectroMagnetic Interference (EMI)
  • Operating Conditions
    • Junction temperature (TJ ) range: -40°C to +125°C
    • SAM9X7x-I devices ambient temperature (TA) range: -40°C to +85°C
    • SAM9X7x-V devices ambient temperature (TA) range: -40°C to +105°C
  • Qualification – AEC-Q100 Grade 2 ([-40°C to +105°C] ambient temperature) applies to -V/4PBVAO devices only 
  • Packages
    • 11 x 11 mm2 , 0.65-mm pitch, 240-ball BGA optimized for standard class PCB layout (down to four layers)
    • 9 x 9 mm2 , 0.5-mm pitch, 256-ball BGA for space-constrained applications

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