LIN Physical Layer

Last modified by Microchip on 2023/11/09 08:54

In the OSI model, the Physical Layer is concerned with "putting the bits on the wire."

The Local Interconnect Network (LIN) physical layer is based on ISO 9141 (the K-line bus). It consists of the bidirectional bus line LIN which is connected to the transceiver of every bus node, and is connected via a termination resistor and a diode to the positive battery node, VBAT.

​A detailed description of the LIN Physical Layer is provided in Section 6 of "LIN Specification Package Revision 2.2A".


The LIN bus operates between 9 V and 18 V. Typically, the microcontroller LIN I/O pins voltage levels are adjusted to the LIN bus levels by a transceiver. This allows the microcontroller to operate at 3/5 V levels, while the bus operates at higher levels.

Transceiver node

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Simplified LIN ECU Node

Electronic Control Unit (ECU) is a generic term for any embedded system that controls one or more of the electrical system or subsystems in a transport vehicle.

Transceiver node spec

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A "Master" LIN ECU Node (From the LIN Standard)

Diodes Dser_intand Dser_master are mandatory to prevent uncontrolled powering of the ECU node from the bus line, in the case of a battery loss.

LIN cluster

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LIN Cluster

A LIN cluster is composed of a single-wire bus, a Master node and up to 15 Slave nodes.

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Key Characteristics

  • Single Master, Multiple Slaves (up to 15 Slaves)
  • Single wire plus ground signaling: (VBAT, GND, LIN (9 V-18 V))
  • From 1 kbit/s up to 20 kbit/s
  • Dominant/Recessive bits (like the CAN bus)
  • Total length of bus line: 40 meters max
  • Terminations: Master 1 kΩ, Slave 30 kΩ

LIN signaling

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It was the goal of the LIN design to achieve a simplistic wiring topology. The simple single-wire bus connects to each node in the cluster and switches from ground to battery-level voltage as shown:

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Signal Levels

  • Dominant - Bus LOW - Logic 0
  • Recessive - Bus HIGH - Logic 1

A LIN Network implements Wired and Signalling:

  • All nodes must be HIGH (Recessive) in order to transmit a Logic 1
  • Only one node LOW (Dominant) will transmit a Logic 0

LIN signaling

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Typical LIN Node Configurations

There are a variety of LIN ICs available to implement in a LIN Node. The following schematic diagrams outline some common configurations.

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Stand Alone Transceiver

For example, MCP2003B

stand alone transceiver

Note: The MCU UART Peripheral should be LIN-capable, as described in the device datasheet.

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Stand Alone Transceiver with Built-in Voltage Regulator

For example, MCP2021A

mini system basis

These ICs are also referred to as "Mini LIN System Basis Chips."

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Stand Alone Transceiver with Built-in Voltage Regulator and Watchdog Timer

For example, MCP2050

system basis chip

These ICs are also referred to as "LIN System Basis Chips."

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System-in-Package (SiP)

For example, PIC16F1829LINATA6616C, and ATSAMHA1G16A
These contain an MCU + complete LIN System Basis Chip functionality.

system in package

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Transient Voltage Protection (Load Dump)

An external 60 V Transient Suppressor (TVS) diode, between VBB and ground, with a 50 Ω Transient Protection Resistor (RTP) in series with the battery supply and the VBB pin serve to protect the device from power transients and ESD events. While this protection is optional, it is considered good engineering practice, as shown in the following example circuit using MCP2003B:

transient protection

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