Fault Detection Operation

Last modified by Microchip on 2024/01/19 00:11

Cycle-by-Cycle Operation

Faults can be detected using cycle-by-cycle operation. See Figure 1. The upper waveform represents the fault's active signal. An example of the fault could be over-current. When the current limit threshold is reached, the Pulse-Width Modulation (PWM) duty cycle can be controlled by the built-in cycle-by-cycle current-limit mode and the analog comparator. When the current-sense signal at the input of the analog comparator exceeds the programmed comparator threshold, the PWM output is immediately terminated for the remainder of the PWM cycle.

At each PWM period boundary (shown by the dashed lines), the PWM tries to start again. When the fault condition is still present, no PWM signal will appear at the output. As soon as the fault source is removed, at the beginning of the following PWM period boundary, the PWM signal will again start running normally at the output.

fault cycle by cycle graphic

Figure 1

If a fault condition is detected, it is often essential that the system be turned off to prevent damage. The PWM module on the dsPIC33FJ16GS504 has a built-in latched fault mode. Using the latched fault mode, certain faults will immediately disable the PWM outputs with no software overhead.

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Fault Operation Example

A possible use of the cycle-by-cycle and latched operation is shown in Figure 2. When the system is turned on, there could be a high level of inrush current flowing into the system. In this case, we can enable the cycle-by-cycle operation so that we could prevent the system from being damaged. At the same time, we allow the current (and voltage) to reach their steady-state value safely.

fault cycle by cycle example graphic

Figure 2

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Managing Fault Conditions in Multi-Converter Applications

Microchip's dsPIC® Digital Signal Controllers (DSCs) can manage fault conditions in a multi-converter environment. Suppose you have a dsPIC driving two converters using PWM1 and PWM2. At a certain time, a fault event occurs in PWM1. The fault circuit will immediately shut down the PWM. See Figure 3. After some time, the fault source is removed. The designer can configure the unit to not restart immediately, but to wait for a certain amount of time (programmable), and then restart the operation of PWM1. Meanwhile, PWM2 has not been affected at all by the fault on PWM1.

fault multi converter graphic

Figure 3

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Over-temperature Protection

Over-temperature protection must be enabled to prevent damage to the system in the event of:

  • Insufficient airflow in the system caused by a failure of the cooling fan.
  • Operation of the system at a high ambient temperature.

Temperature sensors can be implemented and placed near the power conversion circuit by outputting an analog voltage proportional to the measured temperature. The output of the temperature sensor is connected to an analog input of the dsPIC DSCs.

The Printed Circuit Board (PCB) temperature is measured in the ADC Interrupt Service Routine (ISR) and checked for over-temperature protection in the fault loop. The maximum temperature set point is configurable. If the measured temperature exceeds the maximum set point, a fault is generated and the PWM outputs are turned off.

The ADC ISR is the heart of the control software of dsPIC DSCs in power conversion applications. All control loops are executed in the ISR. Since faster control loop execution is desired for the best system performance, functions executed in this routine are written in Assembly language. The ADC ISR has the highest priority of execution. The ADC module is configured to generate interleaved interrupt requests in order to execute multiple control loops within the same ISR.

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Under-voltage (Over-current)/Over-voltage Protection

Every power conversion application is designed to operate within a range of input voltages. For example, the Power Factor Correction (PFC) Boost Converter is designed to operate normally for input voltages in the range of 85V – 265V. In the event of an under-voltage condition, the circuit components will undergo excessive stress due to the additional current drawn by the system to deliver maximum output power. Therefore, under-voltage and over-voltage faults must be implemented to prevent damage to the system and load.

In the event of an over-voltage condition, the input voltage may exceed the device ratings. There are instances when the power grid may exhibit momentary voltage fluctuations, which must be ignored by the system. The input AC voltage protection is implemented in software by calculating the average input voltage in the ADC ISR. The average input voltage is calculated as a part of the PFC control scheme and is checked in the fault loop to detect a sustained under-voltage/over-voltage condition. The first time an under-voltage/over-voltage condition is detected, a counter is incremented. If the condition remains for an extended period of time (programmable), a fault is generated and the outputs are turned off.

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