PWM Peripheral

Last modified by Microchip on 2024/01/15 16:12

The Pulse Width Modulation (PWM) module in the dsPIC33F/E is designed for applications that require:

  • High-resolution at high PWM frequencies
  • The ability to drive Standard, Edge-Aligned, Center-Aligned Complementary mode and Push-Pull mode outputs
  • The ability to create multiphase PWM outputs
  • Frequency Resolution of 1.04 ns
  • Duty Cycle Resolution of 1.04 ns
  • Phase Shift Resolution of 1.04 ns
  • Dual Trigger from PWM to ADC
  • PWM Capture Feature
  • On-the-Fly PWM Frequency, Duty Cycle and Phase Shift Changes

The PWM module features include:

  • Two to four PWM generators within four to eight outputs
  • Dead time for rising and falling edges
  • Multiple PWM Output Waveform Mode support:
    • Standard Edge-Aligned
    • Complementary Outputs
    • Push-Pull
    • Multiphase
    • Variable Phase
    • Current Reset
    • Current-Limit

Two common medium power converter topologies are push-pull and half-bridge. In push-pull type power converters, there are several synchronous rectifier topologies. These designs require the PWM output signal to be switched between alternate pins, as provided by the Push-Pull PWM mode. Phase-shifted PWM describes the situation where each PWM generator provides outputs, but the phase relationship between the generator outputs is specifiable and changeable. PWM peripherals in the dsPIC are remappable. Figure 1 shows the remappable peripherals of the dsPIC33F series.

remappable peripherals of dsPIC33F series

Figure 1

The conceptual block diagram of the PWM peripheral in the dsPIC devices is shown in Figure 2. The peripheral has up to four PWM generators (see four colored blocks), and up to eight PWM output pins. The actual number of blocks depends on the specific part number. All the generators have equal capabilities.

Note that each PWM unit has two output pins, named PWMxL and PWMxH. According to the user's needs, the two pins of each unit can work together in complementary mode or can be completely independent, i.e., each unit can generate two PWM signals independently.

conceptual block diagram of the PWM peripheral in the dsPIC devices

Figure 2

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PWM Period and Duty Cycle Management

Definition of the PWM Period

Figure 3 shows the high-level circuit schematic of an individual PWM unit. Each unit can select, independently from any other, a global register to define the PWM period (MASTER PERIOD) or a local register (PHASEx or SPHASEx) to set the PWM period. All units using the MASTER PERIOD will have the same PWM frequency. If the local registers are selected, the user has two choices:

  • Select the PWM period with the PHASEx REGISTER for the two pins.
  • Select two different PWM periods (using the PHASEx REGISTER for the H output) and the (SPHASEx REGISTER for the L output). The two frequencies are completely independent.
high-level circuit schematic of an individual PWM unit

Figure 3

In some operational modes, the (S)PHASEx registers can be used to change the relative phase of the signals from the unit. One typical application of this feature is the implementation of Zero Voltage Transition (ZVT) control strategy.

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Definition of the Duty Cycle

The duty cycle definition mimics the PWM period definition. The user can select the global MASTER DUTY REGISTER or choose one or two local duty cycle registers (PDCx and SPDCx REGISTERS). As already stated, the maximum resolution of the PWM peripheral is always 1.04 ns; this is true for the PWM period, duty cycle, and phase shift.

One key feature is the possibility of synchronizing the operation of the ADC to the operation of the PWM. Often it is advantageous to read the current (and/or voltage) in a very specific instant in time within the PWM period. The peripheral is capable of generating up to two trigger signals to the ADC to start sampling at any desired point within the period

All registers can be changed on the fly; they can also be synchronized with the PWM period edges. You are completely free to select the option that better fits your application.

The second high-level circuit schematic is the Current-Limit, Fault Override, and Routing Logic, which is dedicated to controlling the output operations.

High Level Circuit Schematic - Logic

Figure 4

The following functionalities are implemented:

  • Output logic: Controls the normal operation of the PWM output pins.
  • Override logic: Sometimes the user wants to disconnect the output pin from the PWM generator. This can be useful when the output PWM waveform has to be replaced by a fixed value, either low or high. This may be used to give the correct polarities to a synchronous buck converter when it is off (the pass transistor should be off, but the freewheeling transistor could be on to ensure a zero V output level). Each pin can be overridden individually.
  • Current limit: It is possible to change the duty cycle of the PWM signal as a function of the current flowing into the inductor. This is called current limit.
  • Fault logic: An example of a fault condition could be an over-current or over-voltage in some section of the circuit. Each PWM unit can receive a fault condition signal from several different sources. The effect will be to immediately shut down the PWM outputs (the user can define what must be the status of the output pins in this condition, high or low). The delay between the fault signal going active and the output pins being disabled is the propagation delay through a few logical gates (a few tens of ns). As an additional feature, the unit can automatically resume from fault at the beginning of each PWM period, or it can resume only via a direct intervention of the user.

The third layer contains the dead time generators. The feature is important because the two switches of one leg of a bridge should never be on at the same time to avoid shoot-through and possible destruction of the switches. Each unit can generate two different dead time intervals (one for the rising and the other for the falling edges) of variable durations. Dead time will always be automatically added. The resolution for the dead periods is 1.04 ns.

High Level Circuit Schematic - Dead Time

Figure 5

The last high-level PWM circuit block is the Pin Control, which directly controls the pin signals. See Figure 6.

High Level PWM Circuit Block Pin Control Schematic

Figure 6

The Pin Control circuit has a few major functions:

  • Pin Swapping: It is possible to swap the signal from the Low to High pin.
  • Remappable Pins: You can freely define which signals are mapped to which pins. Note that the remapping capability is available also for all other digital pins as well as some internal signals.
  • Complementary Outputs

Application example: Single-Phase Synchronous Buck Converter

The synchronous buck converter is similar to the standard buck converter, except that the catch diode (Schottky diode) is now replaced with a MOSFET. Due to MOSFET's low ON resistance compared to the diode, higher efficiency can be achieved. Figure 7 shows a synchronous buck converter circuit diagram. The two switches are operated as a complementary pair, which can be controlled by the dsPIC PWM module output pins. Dead time control can also be implemented to prevent shoot-through current.

synchronous buck converter circuit diagram

Figure 7

The timing waveform of the complementary PWM outputs is in Figure 8. It can be seen the PWM H and L pins signals. The dead time intervals have been added for both the rising and falling edges to avoid shoot-through.

timing waveform of the complementary PWM outputs

Figure 8

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