16-bit PIC® MCU Instruction Set Architecture Overview

Last modified by Microchip on 2023/11/09 09:00

Programmer's Model

This section provides an overview of the 16-bit programmer's model of the following families of devices:

  • 16-bit Microcontrollers (MCU):
    • PIC24F
    • PIC24H
    • PIC24E
  • 16-bit Digital Signal Controllers (DSC):
    • dsPIC30F
    • dsPIC33F
    • dsPIC33E

Links are provided on this page to the various aspects of the 16-bit family Instruction Set Architecture (ISA):

  • Memory Organization:
    • Address Space (number of locations addressed)
    • Addressability (how many bits per location)
  • Registers:
    • How many? What size? How are they used?
  • Instruction Set:
    • ISA Type, Data Types, Instruction Categories, Addressing Modes, Software Stack Pointer

The main reference for this page is the "16-bit MCU and dsPIC® Programmer's Reference Manual (DS70157)".

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16-bit Core Registers

The 16-bit MCU and DSC devices have sixteen 16-bit working registers, which are memory-mapped to the first 16 words in data memory. Each of the working registers can act as a data, address, or offset register. The 16th working register (W15) operates as a software Stack Pointer for interrupts and calls. Additionally, W0-W3 is used to hold the results of certain DIV and MUL operations as shown in the accompanying image.

Image Showing PIC24 Working Registers and Status Register​​​​​

The core registers in the accompanying image are also available on all 16-bit devices.

Other Core Registers on 16-bit Devices​​​​​

  • CORCON: Used to set the configuration of the CPU. It provides the ability to map program space into data space.
  • PSVPAG: Used to select the 32 kByte region of program memory space that is mapped to the data address space.
  • TBLPAG: Used to hold the upper eight bits of a program-memory address during the table read/write operations.
  • RCOUNT: Contains the loop counter for the REPEAT instruction.
  • PCH:PCL: Program Counter.

Note: Program counter Least Significant Bit (LSb) is always “0” when accessing instructions. The LSb of the program memory address (PC<0>) is reserved as a byte select bit for program memory accesses from data space that use Program Space Visibility (PSV) or table instructions. Instructions exist in program memory user space only (not Configuration space). The program counter uses bits 0 to 22 only for addressing instructions in this space. The Most Significant Bit (MSb) of the program counter (bit 23) will be a “1” when accessing data with Table Read or Table Write operations in Configuration space.

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DSP-Specific Registers

Several of the standard working registers have additional functionality for Digital Signal Processor (DSP) operations as shown in the accompanying image.

DSP Specific Working Registers​​​​​

Additionally, there are several DSP-Specific registers, including two 40-bit accumulators (A & B) available for DSP operations as shown in the accompanying image.

Other DSP Specific Registers​​​​​

  • DCOUNT: Contains the loop counter for hardware DO loops.
  • DOSTART: Contains the starting address for the hardware DO loop.
  • DOEND: Contains the ending address for the hardware DO loop.
  • ACCA/ACCB: 40-bit wide registers, utilized by DSP instructions to perform mathematical and shifting operations.

For more information on 16-bit DSP features, view the DSP Features of the Microchip dsPIC DSC course that is available on Developer Help Skills.

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Instruction Set

ISA Classification Types

CPU instruction set architectures can be classified according to where the operands come from in Arithmetical Logical Unit (ALU) operations. There are four basic classifications:

  • Stack
    • OP1 « The Stack
    • OP2 « The Stack
  • Accumulator-Memory
    • OP1 « Accumulator
    • OP2 « Memory
  • Register-Memory
    • OP1 « CPU Register
    • OP2 « Memory
  • Register-Register (Load/Store)
    • OP1 « CPU Register
    • OP2 « CPU Register

Most MCU CPUs are Register-Memory machines since the speed of the memory technology often matches the CPU speed. These architectures support efficient bit (read/modify/write) operations.

Modern high-performance MCU CPUs are increasingly moving to Load/Store architectures to de-couple the CPU speed from memory speed and use cache memories to enable sustained high CPU performance.

The ISA classification defines the required Addressing modes for the instruction set.

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16-bit ISA Classification

PIC24 and dsPIC implement a hybrid ISA architecture, supporting both Register-Memory and Register-Register operations as shown in the accompanying images.

ALU Data Path for Register-Memory Operations​​​​

Additionally, the 40-bit DSP ALU implements an Accumulator-Memory architecture as described in "DSP Features of the Microchip dsPIC® DSC".

Data Types

The ALU in 16-bit MCU devices (PIC24F/H/E) supports two fundamental data types:

16-bit DSC devices (dsPICxx) support additional DSP data types described in "DSP Features of the Microchip dsPIC® DSC".

In addition to the ALU, 16-bit MCUs and DSCs incorporate a dedicated 17x17 Hardware Multiplier as well as hardware-assisted signed/unsigned 16/16 and 32/16 division operations.

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Instruction Categories

The 16-bit MCU and DSC instruction set provides a rich suite of instructions that support traditional microcontroller applications and a class of instructions that support math-intensive applications. The majority of the instructions are encoded in a single 24-bit word and executed in a single instruction cycle.

Depending on the device family, the 16-bit MCU, and DSC instruction set contains up to 84 instructions, which can be grouped into the functional categories shown in the accompanying table.

Instruction Categories​​​​

Byte operations are indicated by appending a ".B" to the instruction mnemonic, i.e. ADD.B

The instruction set is fully documented in the "16-bit MCU and DSC Programmer's Reference Manual (DS70157)".

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Addressing Modes

The 16-bit MCU and DSC devices support three native Addressing modes for accessing data memory, along with several forms of immediate addressing. Data accesses may be performed using file register addressing, register direct or indirect addressing, and immediate addressing, allowing a fixed value to be used by the instruction. The data memory address range accessed by each Addressing mode is summarized in the accompanying table.

Data Memory Addressing Range for Each Addressing Mode​​​​

File Register (Memory Direct) Addressing

File Register (or Memory Direct) addressing provides the ability to operate on data stored in the lower 8 kBytes of data memory ("NEAR" RAM). Instructions use a predetermined address as an operand.

The majority of instructions that use file register addressing provide byte/word access to the lower 8 kBytes data memory, with the exception of the MOV instruction which provides word access to all 64 kBytes. This allows the loading of the data from any location in data memory to any working register (W0:W15), and storing the contents of any working register to any location in data memory. Examples of File Register addressing are shown in the accompanying image.

Examples of File Register Addressing​​​​

Register Direct Addressing

Register direct addressing is used to access the contents of the 16 working registers (W0:W15). Any working register may be used for any instruction that supports this Addressing mode.

Instructions using this Addressing mode use the contents of the specified working register as operands for the operation to be performed. This Addressing mode supports both byte and word access. Sample instructions that utilize register direct addressing are shown in the accompanying example.

Examples of Register Direct Addressing​​​​

Register Indirect Addressing

Register Indirect addressing is used to indirectly access any location in data memory by treating the contents of a working register as an Effective Address (EA) to data memory. Essentially, the contents of the working register become a pointer to the location in data memory which is to be accessed by the instruction.

Additionally, the contents of the working register may be modified pre- or post-operation, providing an efficient mechanism for processing data stored sequentially in memory. The modes of indirect addressing supported are shown in the accompanying table.

Register Indirect Addressing Modes​​​​

The accompanying examples illustrate indirect addressing with pre/post increment/decrement EA modification.

Examples of Register Indirect Addressing​​​

Immediate Addressing

In immediate addressing, the instruction encoding contains a predefined constant operand which is used by the instruction. The size of the immediate operand varies with the instruction type. Constants of size 1-bit, 4-bit, 5-bit, 6-bit, 8-bit, 10-bit, 14-bit, and 16-bit are allowed, depending on the instruction. Constants may be signed or unsigned.

The accompanying example illustrates some examples using Immediate Addressing.

Examples of Immediate Addressing​​​

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Software Stack

The 16-bit MCU and DSC devices feature a software stack that facilitates function calls and exception handling. W15 is the default Stack Pointer (SP). After any Reset, it is initialized to 0x0800 (0x1000 for PIC24E and dsPIC33E devices). This ensures that the SP will point to valid RAM and permits stack availability for exceptions, which may occur before the SP is set by the user software. The user may reprogram the SP during initialization to any location within the data space.

The SP always points to the first available free word (Top-of-Stack) and fills the software stack, working from lower addresses towards higher addresses. It pre-decrements for a stack POP (read) and post-increments for a stack PUSH (write).

The software stack is manipulated using the PUSH and POP instructions. The PUSH and POP instructions are the equivalent of a MOV instruction, with W15 used as the destination pointer. For example, the contents of W0 can be PUSHED onto the Top-of-Stack (TOS) by:


This syntax is equivalent to:

MOV W0,[W15++]

The contents of the TOS can be returned to W0 by:


This syntax is equivalent to:

MOV [--W15],W0

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PIC24E and dsPIC33E ISA Enhancements

This section describes the ISA enhancements that are available in the PIC24E and dsPIC33E families of devices.

EDS Addressing

The Base Data Space address is used in conjunction with a read or write page register (DSRPAG or DSWPAG) to form an EDS address, which can also be used for PSV access.


The EDS can be addressed as 8 MWords or 16 MBytes. Refer to Section 3, “Data Memory” (DS70595) in the “dsPIC33E/PIC24E Family Reference Manual” for more details on EDS, PSV, and table accesses. Please visit the Extended Data Space page to learn more about EDS addressing.

Other Extensions

A variety of other extensions have been implemented:

  • Automatic Mixed-Sign Multiplication Mode (dsPIC33E)
  • MCU Multiplications with 16-bit Result
  • Hardware Stack for DO Loops (dsPIC33E)
  • DSP Context Switch Support (dsPIC33E)
  • Extended CALL and GOTO instructions
  • New Compare-Branch (CPBxx) instructions (PIC24E/dsPIC33E)

For details on these, please review the "16-bit MCU and DSC Programmer's Reference Manual (DS70157)".

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