Doze, Idle, and Sleep Mode in 16-bit MCUs and DSCs
Doze, Idle, and Sleep modes allow the system clock to be manipulated by an application in order to reduce power consumption. Sleep has an additional option: Low-Voltage Sleep.
| Mode | CPU Clock (Fcy) | System Clock (Fosc) | Peripheral Clock (Fp) | All Memory Retained |
|---|---|---|---|---|
| Doze | Slower | Full Speed | Full Speed | Yes |
| Idle | Stopped | Full Speed | Full Speed | Yes |
| Sleep | Stopped | Stopped | Stopped | Yes |
| Low Voltage Sleep | Stopped | Stopped | Stopped | Yes |
Doze Mode
Doze mode allows the application program to slow down the CPU clock while leaving the peripheral clock unchanged. When switching to Doze mode, no adjustment is needed to the individual peripheral configuration registers. The operation of the peripherals is not affected by the change in the CPU clock speed.
Entering Doze Mode
Doze Mode is controlled by the upper five bits of the Clock Divider Register CLKDIV<15:11>.
CLKDIV: Clock Divider Register
| bit 15 | ROI: Recover on Interrupt 1 = Interrupts clear the DOZEN bit and reset the CPU clock ratio to 1:1 |
| bit 14-12 | DOZE<2:0>: CPU Clock Ratio Select bits 111 = 1:128 |
| bit 11 | DOZEN: DOZE Enable bit 1 = CPU clock specifed by DOZE<2:0> |
- The Doze Enable (DOZEN) bit causes the device to enter Doze mode.
- When DOZEN is set, the speed of the CPU is cycled down by the amount specified by DOZE<2:0>.
- The user has the option of restoring the CPU clock to the speed set by the configuration bits when an interrupt occurs. This allows interrupts to be processed at full speed. The Recover on Interrupt (ROI) bit controls the state of the clock for interrupt processing.
Exiting Doze Mode
Doze mode is exited by clearing the DOZEN bit.
Idle Mode
Idle mode turns off clock to the CPU but leaves the clock to the peripherals unchanged. In Idle mode, the system oscillator is left running and the data in all memory locations is retained.
Entering Idle Mode
A device is put into Idle mode by executing the PWRSAV assembly instruction with the suffix #1.
; Alternatively, if the appropriate INC file in .included:
PWRSAV #IDLE_MODE
The MPLAB® XC16 C Compiler defines a macro for PWRSAV #IDLE_MODE.
//…
Idle(); // enter Idle mode
//…
Exiting Idle Mode
The Idle mode will end and the CPU will execute the instruction immediately following the PWRSAV instruction upon the following conditions:
- A Reset condition, other than a Power-On Reset.
- A Watchdog Timer overflow.
- An interrupt request occurs with a priority less than or equal to the current priority of the CPU.
If an interrupt occurs with a priority higher than the present CPU priority, the CPU wakes up and begins execution with the interrupt service routine.
Sleep Mode
Sleep mode turns off the system clock. If enabled, the WDT will run off the LPRC. The CPU and all peripherals requiring the system clock will cease operation. The contents of the memory and registers are maintained in Sleep mode.
Entering Sleep Mode
A device is put into Sleep mode by executing the PWRSAV assembly instruction with the suffix #0.
; Alternatively, if the appropriate INC file in .included:
PWRSAV #SLEEP_MODE
The MPLAB® XC16 C Compiler defines a macro for PWRSAV #SLEEP_MODE.
//…
Sleep(); // enter Sleep mode
//…
Exiting Sleep Mode
Sleep mode will end and the CPU will execute the instruction immediately following the PWRSAV instruction upon the following conditions:
- A Reset condition, other than a Power-On Reset.
- A WDT overflow.
- Any interrupt request occurs.
Delay in Exiting Sleep Mode
The delay associated with waking up from Sleep will vary depending upon the oscillator being used. For most oscillator settings, the delay in waking up from Sleep is the same as when the device is first powered on. Please consult the datasheet of the device you are using to determine the specific delay for the part you are using.
Low-Voltage Sleep Mode
Low-Voltage Sleep mode stops the system clock in the same way as the Sleep mode. Low-Voltage Sleep mode uses a low-voltage regulator to power the core. This mode uses less power than the Sleep mode but takes longer to wake up from sleep due to the voltage regulator.
Entering Low Voltage Sleep
The low-voltage regulator is controlled by the LPCFG/LVRCFG configuration bit (also designated as LVRCFG in some devices) and the Low-Voltage Enable bit (RETEN/LVREN), and Reset and System Control register (RCON). The LPCFG/LVRCF configuration bit makes the low-voltage regulator available to be controlled by RCON.
With the LPCFG/LVRCFG configuration bit set, the following sequence of instructions will put the device into Low-Voltage Sleep mode:
- Setting the LVREN bit in RCON.
- Executing PWRSAV instruction with the suffix #0.
BSET RCON LVREN
PWRSAV #SLEEP_MODE
With MPLAB® XC16 C Compiler:
//…
RCONbits.LVREN = 1 ;
Sleep(); // enter Sleep mode
//…
Exiting Low-Voltage Sleep
Low-Voltage Sleep mode will end and the CPU will execute the instruction immediately following the PWRSAV instruction upon the following conditions:
- A Reset condition, other than a Power-On Reset.
- A WDT overflow.
- Any interrupt request.