Vbat for 16-bit MCUs
Vbat mode is a hardware-based power mode that maintains critical operations when a power loss occurs on Vdd. To enable Vbat mode, a back-up power source must be connected to the Vbat pin. In Vbat mode the Real-Time Clock/Calendar (RTCC) can run when there is no power on Vdd.
Running with Vdd
When Vdd is present, an onboard switch directs the input voltage to the power regulator. The regulator supplies power to the entire MCU core and peripheral registers.
Loss of Vdd
Vbat mode is entered whenever the power source is removed from Vdd. The on-chip power switch detects the power loss from the Vdd and connects the Vbat pin into a low voltage regulator. The low power regulator supplies power to the RTCC (if enabled) and both Deep Sleep Retention registers (DSGPR0 and DSGPR1).
No peripherals other than the RTCC receive power in Vbat mode. The contents of memory locations and registers other than the DSGPR0 and DSGPR1 are not retained.
When Vdd is restored
When Vdd is restored the device experiences a Power On Reset (POR):
- All registers, except DSGPR0 and DSGPR1, are returned to their reset state.
- The system oscillator is initialized per the configuration bits.
- The program counter is set to execute the instruction located at 0x000.
The contents of the DSGPR0 and DSGPR1 are retained through the POR. These registers can be read at any time by the software.
Context Saving before Vbat is Entered
The loss of Vdd is typically a spurious and unplanned event. Applications requiring data other than RTCC be retained during a power loss must proactively save the data. The data can be saved to off-chip non-volatile memory or to the Deep Sleep Registers.
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