PIC32MX Coprocessors

Last modified by Microchip on 2023/11/09 09:00

The MIPS® standard register set omits many features needed for a real MCU (i.e. exception handling), however, op-codes are reserved and instruction fields are defined for up to four coprocessors which may be included in a MIPS implementation:

  • Coprocessor 0 (CP0) is incorporated on the CPU chip and supports the virtual memory system and exception handling. CP0 is also referred to as the System Control Coprocessor.
  • Coprocessor 1 (CP1) is reserved for the floating-point coprocessor, the FPU.
  • Coprocessor 2 (CP2) is available for specific implementations.
  • Coprocessor 3 (CP3) is reserved for the floating-point unit in Release 1 implementations of the MIPS64® Architecture and in all Release 2 (and subsequent releases) implementations of the architecture.

PIC32MX Coprocessor 0 (CP0) Registers

The MIPS M4K® CPU in the PIC32MX uses a special register interface to communicate status and control information between system software and the CPU. This interface is called Coprocessor 0, or CP0. The features of the CPU that are visible and controllable through the Coprocessor 0 register interface are:

  • Core timer
  • Interrupt and exception control
  • Virtual memory configuration
  • Shadow register set control
  • Processor identification
  • Debugger control
  • Performance counters

System software accesses the registers in CP0 using coprocessor instructions such as mfc0 (move from coprocessor 0 register) and mtc0 (move to coprocessor 0 register).

The following example clears the core timer counter register and initializes its period register with the value in a0:

mtc0    zero, Count
mtc0    a0, Compare

The following example reads the value of the exception cause register into s0:

mfc0    s0, Cause

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Coprocessor Load and Store Instructions

For CP0 only, the mtc0 and mfc0 instructions must be used to write and read the CP0 registers.

The loads and stores for the remaining coprocessors are implemented via the lwcx and swcx instructions, for example:

  • lwc1: Load word from Coprocessor 1 register
  • swc1: Store word to Coprocessor 1 register

​Table 2-7 in the PIC32MX CPU Reference Manual outlines the CP0 registers found on PIC32MX devices and is reproduced below.

The CP0 registers found on PIC32MX devices

Some CP0 register numbers have multiple register entries. The following nomenclature is used to identify specific registers:

  • Status Register: CP0 Register 12, Select 0
  • IntCtl Register: CP0 Register 12, Select 1

CP0 load/store assembly instructions mfc0/mtc0 support encoding of the Select# to enable selection of all CP0 registers.

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Which CP0 Registers Are Relevant When?

  • After power-up:

    • You'll need to setup Statusxxx bits to get the CPU into a workable state for the rest of the bootstrap procedure.
    • The first Config register has a few writable bits which you may need to set in order for anything to work.

​See the MPLAB® XC32 Compiler User's Guide, sec 14.3.5  for a discussion on which CP0 registers are initialized by the start-up code as well as their initialized values.

  • Handling an exception:
    • On entry, no program registers have been saved, only the restart address in EPC.
    • Handler code must save EPC and Status context for nested interrupt operation.
    • For general exceptions, consult the Cause register to find out what kind of exception it was and dispatch accordingly.
  • Returning from exception:
    • Control must eventually be returned to the value stored in EPC on entry.
    • The Status register must be adjusted on exit, restoring the user-privilege CPU state (if required) and re-enabling exceptions respectively.

​The return-from-exception instruction eret clears the StatusEXL bit (re-enabling exceptions), and branches to the location saved in EPC.

  • Interrupt exceptions:
    • StatusIE: acts as the master enable for hardware/software interrupt exceptions.
    • StatusIPL: contains the current CPU priority level. Software can write to these bits at any time, changing the priority of the CPU.

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