PIC32MX Shadow Register Set

Last modified by Microchip on 2023/11/09 09:00

The PIC32 processor implements one or more copies of the General Purpose Registers (GPR) for use by high-priority interrupts. The extra banks of registers are known as shadow register sets. When a high-priority interrupt occurs, the processor automatically switches to a shadow register set without software intervention. This reduces overhead in the interrupt handler and reduces effective latency.

Interrupt Latency Reduction

The shadow register sets are controlled by registers located in the System Coprocessor (CP0) as well as the interrupt controller hardware located outside of the CPU core.

​PIC32MX application software is responsible for enabling use of the shadow register set via appropriate definition of the ISR handler function, as described here.

​PIC32MX795F512L implements 1 shadow register set. Please refer to the device data sheet for information as to how many shadow register sets are available in your device.

​PIC32MX application software must take care not to define more than 1 ISR handler as using the shadow register set.

​PIC32MX1xx/2xx/530/550/570 devices do not implement a shadow register set.

Basic Operation

An interrupt exception request is decoded by the interrupt controller. The vector number, requested priority level and shadow register set numbers are provided to the CPU core as shown below:

PIC32MX Shadow Register Structure

The shadow register set number is then written to the SRSCtlEICSS bit-field, which is used to select the "current shadow set" for the interrupt.

The MIPS32® M4K® core then uses this information to perform the following:

  • The current GPR Bank ID is copied into the SRSCtlPSS field of the SRSCtl register. This is the Previous Shadow Set (PSS) ID to be recovered later when the interrupt exception request is completed.
  • The GPR set ID pulled from SRSCtlEICSS is copied into the SRSCtlCSS field of the SRSCtl register. This now specifies the Current Shadow Set (CSS).
  • Execution of the interrupt exception handler proceeds to completion, and an IRET instruction is executed.
  • The core then copies the values from the SRSCtlPSS bit field into the SRSCtlCSS bit field and execution resumes from the point at which the interrupt exception was issued.