PIC32MX Memory Map
The following diagram shows an example of the memory map for a PIC32MX device (PIC32MX795F512L) with 512 KB of program memory for a typical application running in Kernel mode after the start-up code has executed:
![memory map for a PIC32MX device](/xwiki/bin/download/products/mcu-mpu/32bit-mcu/PIC32/mx-arch-cpu-overview/memory-organization-overview/memory-map/WebHome/memory-map.png?rev=1.1)
Figure 1
The segments, KSEG0 and KSEG1, both translate to physical address 0x0 and include all of program Flash and data memory; however, KSEG0 is cacheable and KSEG1 is not.
The uncached region, KSEG1, also provides virtual address space translation to the Special Function Registers (SFRs) for PIC32MX family devices.
KSEG0/KSEG1 Code Space Mapping Detail
While difficult to see from Figure 1, remember that the mapped KSEG0/KSEG1 addresses don't occupy the same physical addresses!
The following diagram shows where cacheable/non-cacheable KSEG0/KSEG1 virtual memory segments are mapped into physical memory on PIC32MX795F512L:
![code-space-mapping-mx795.png](/xwiki/bin/download/products/mcu-mpu/32bit-mcu/PIC32/mx-arch-cpu-overview/memory-organization-overview/memory-map/WebHome/code-space-mapping-mx795.png?rev=1.1)
Figure 2