PIC32MX Memory Map

Last modified by Microchip on 2023/11/09 09:00

The following diagram shows an example of the memory map for a PIC32MX device (PIC32MX795F512L) with 512 KB of program memory for a typical application running in Kernel mode after the start-up code has executed:

memory map for a PIC32MX device

Figure 1

The segments, KSEG0 and KSEG1, both translate to physical address 0x0 and include all of program Flash and data memory; however, KSEG0 is cacheable and KSEG1 is not.

The uncached region, KSEG1, also provides virtual address space translation to the Special Function Registers (SFRs) for PIC32MX family devices.

Note that XC32 will place all C-runtime startup code starting at virtual address 0xBFC00000 in KSEG1. Recall that this region (KSEG1) is the only one guaranteed to behave properly from the system reset. 0xBFC00000 is translated (via a fixed mapping) to the physical address 0x1FC00000 (Boot Flash Memory).

Physical addresses are used by the DMA controller, the Flash controller (when programming Flash memory), and when defining protected memory regions.

Virtual addresses are used by the CPU for fetching and reading or writing data or peripheral SFRs.

Keep this in mind when setting up these modules.

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KSEG0/KSEG1 Code Space Mapping Detail

While difficult to see from Figure 1, remember that the mapped KSEG0/KSEG1 addresses don't occupy the same physical addresses!

The following diagram shows where cacheable/non-cacheable KSEG0/KSEG1 virtual memory segments are mapped into physical memory on PIC32MX795F512L:


Figure 2

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