PIC32MX Oscillator - USB Phased-Lock Loop

Last modified by Microchip on 2023/11/09 09:00

USB PLL Configuration

USB PLL Configuration

The USB Clock can be derived from the 8 MHz internal FRC oscillator, 48 MHz POSC, or the USB PLL. For normal operation, the USB module requires an accurate 48 MHz clock.

The USB PLL input divider must be configured to provide 4 MHz to the multiplier. This divider is controlled by the UPLLIDIV setting with the following options:
÷1, ÷2, ÷3, ÷4, ÷5, ÷6, ÷10, ÷12

The internal 8 MHz FRC oscillator is available as a clock source to detect any USB activity during USB Suspend mode and bring the module out of the Suspend mode. This lowers power consumption while in Suspend mode.

The default USB PLL input divider and USB PLL enable can be configured at program time only. The USB clock source can be configured with the following MPLAB® Harmony function at run-time.

// if POSC = 12, default USB PLL input divide = 3
#pragma config UPLLIDIV = DIV_3
// default USB PLL enabled
#pragma config UPLLEN = ON
// following functions select POSC or FRC as input for the USB clock at run-time
// use for lower power during Suspend