PIC32MZ Addressing Modes

Last modified by Microchip on 2023/11/09 09:01

Memory Loads/Stores

For loading and storing to memory, MIPS32® Central Processing Units (CPUs) implement only one addressing mode: Base Address Plus Displacement.

For example, any load or store machine instruction can be written:

lw     $1, offset($2)

You can use any of the CPU Genreral Purpose Registers (GPRs) for the destination and source. The offset is a signed, 16-bit number (-32768 to +32767). In this example, the program address used for the load is the sum of $2 and the offset.

This addressing mode is sufficient to pick out a particular member of a C structure, or of a particular array element. It is also enough to provide a reasonable-sized global area around the gp value for access to static and extern variables.

Other, more complex memory addressing modes are implemented by the assembler as a sequence of instructions.

Register Loads/Stores

For register loading/storing, MIPS32 Arithmetical Logical Unit (ALU) instructions implement Register-Direct Addressing, whereby the register numbers are encoded directly in the instruction.

Many ALU operations are 3-operand, with the result register and operands shown in the same order you'd use to write the operation in C or any other algebraic language, so:

subu     $1, $2, $3

means exactly:

$1 = $2 - $3