PIC32MZ Oscillator - System Clock (SYSCLK)

Last modified by Microchip on 2023/11/10 11:08

System Clock (SYSCLK) Generation

SYSCLK diagram

The System Clock (SYSCLK) provides the time base for the peripheral clocks, Direct Memory Access (DMA), interrupts, and Flash. SYSCLK is determined from one of the input clocks: SPLL, POSC, FRCDIV, LPRC, BFRC, and SOSC.

The PIC32MX uses SYSCLK to drive the core. This is NOT true for the PIC32MZ. The PIC32MZ core clock is provided by Peripheral Bus Clock #7 (PBCLK7).

You cannot choose to use the BFRC for SYSCLK. Only the hardware will use this when the Fail-Safe Clock Monitor (FSCM) detects a problem.

The default configuration for SYSCLK is programmable and can also be changed at run-time. See the code examples below.

// default system clock = FRCDIV
#pragma config FNOSC = FRCDIV
// default system clock = SPLL
#pragma config FNOSC = SPLL
...    
// run-time config SYSCLK = FRCDIV
PLIB_OSC_SysClockSelect(OSC_ID_0, OSC_FRC_BY_FRCDIV);
// run-time config SYSCLK = POSC with SPLL
PLIB_OSC_SysClockSelect(OSC_ID_0, OSC_PRIMARY_WITH_PLL);